x86: Refactor GDT initialization code
This patch refactors the GDT initialization code in more of a self-documenting style.
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@ -32,6 +32,20 @@
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#define NUM_DESC 3
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#define GDT_IDX_NULL 0
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#define GDT_IDX_CODE 1
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#define GDT_IDX_DATA 2
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/* All code in the x86 port of Contiki runs at ring (privilege) level 0 */
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#define PRIV_LVL 0
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/* Compute GDT selector from descriptor index and requested privilege level */
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#define GDT_SEL(IDX, RPL) (((IDX) << 3) | (RPL))
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#define GDT_SEL_NULL GDT_SEL(GDT_IDX_NULL, 0)
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#define GDT_SEL_CODE GDT_SEL(GDT_IDX_CODE, PRIV_LVL)
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#define GDT_SEL_DATA GDT_SEL(GDT_IDX_DATA, PRIV_LVL)
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/* Each define here is for a specific flag in the descriptor. Refer to Intel
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* Combined Manual (Intel 64 and IA-32 Architectures Software Developer's
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* Manual), Vol. 3, Section 3.4.5 for a description of each flag.
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@ -110,27 +124,25 @@ gdt_init(void)
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gdtr.base = (uint32_t) &gdt;
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/* Initialize descriptors */
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set_descriptor(0, 0, 0, 0);
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set_descriptor(1, 0, 0x0FFFFF, GDT_CODE_PL0);
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set_descriptor(2, 0, 0x0FFFFF, GDT_DATA_PL0);
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set_descriptor(GDT_IDX_NULL, 0, 0, 0);
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set_descriptor(GDT_IDX_CODE, 0, 0x0FFFFF, GDT_CODE_PL0);
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set_descriptor(GDT_IDX_DATA, 0, 0x0FFFFF, GDT_DATA_PL0);
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/* Load GDTR register and update segment registers.
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*
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* In protected mode, segment registers should be loaded according to
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* the offset in GDT. So DS, SS, ES, FS and GS registers should be
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* loadded with 0x10 while CS with 0x08. CS register cannot be changed
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* directly. For that reason, we do a far jump.
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* CS register cannot be changed directly. For that reason, we do a far jump.
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*/
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__asm__ ("lgdt %0\n\t"
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"jmp $0x08, $1f\n\t"
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__asm__ ("lgdt %[_gdtr_]\n\t"
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"jmp %[_cs_], $1f\n\t"
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"1:\n\t"
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"mov $0x10, %%ax\n\t"
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"mov %%ax, %%ds\n\t"
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"mov %%ax, %%ss\n\t"
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"mov %%ax, %%es\n\t"
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"mov %%ax, %%fs\n\t"
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"mov %%ax, %%gs\n\t"
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"mov %[_ds_], %%ds\n\t"
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"mov %[_ds_], %%ss\n\t"
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"mov %[_ds_], %%es\n\t"
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"mov %[_ds_], %%fs\n\t"
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"mov %[_ds_], %%gs\n\t"
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:
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: "m" (gdtr)
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: [_gdtr_] "m" (gdtr),
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[_cs_] "i" (GDT_SEL_CODE),
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[_ds_] "r" (GDT_SEL_DATA)
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);
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}
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