this does 127 B packets as fast as possible (with these settings).
Transmitts are every 5.8ms and are 4.48ms long
This commit is contained in:
parent
8e3c2a8622
commit
5c20312744
100
lib/maca.c
100
lib/maca.c
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@ -15,7 +15,8 @@
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#endif
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#ifndef RECV_SOFTIMEOUT
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#define RECV_SOFTIMEOUT 2500000 /* 10 sec */
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//#define RECV_SOFTIMEOUT 4096 /* about 3.5 128 byte packets */
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#define RECV_SOFTIMEOUT 10000 /* about 3.5 128 byte packets */
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#endif
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#define MACA_CLOCK_DIV 95
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@ -36,7 +37,9 @@ static volatile uint8_t last_post = NO_POST;
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#define safe_irq_disable(x) volatile uint32_t saved_irq; saved_irq = *INTENABLE; disable_irq(x)
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#define irq_restore() *INTENABLE = saved_irq
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void print_packets(char *s) {
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#define print_packets(x) Print_Packets(x)
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void Print_Packets(char *s) {
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volatile packet_t *p;
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int i = 0;
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printf("packet pool after %s:\n\r",s);
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@ -87,6 +90,8 @@ void free_packet(volatile packet_t *p) {
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volatile packet_t* get_free_packet(void) {
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volatile packet_t *p;
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volatile uint32_t i;
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safe_irq_disable(MACA);
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p = free_head;
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@ -95,11 +100,44 @@ volatile packet_t* get_free_packet(void) {
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free_head->right = 0;
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}
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print_packets("get_free_packet");
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for(i=0; i<9783; i++) { continue; }
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// print_packets("get_free_packet");
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irq_restore();
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return p;
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}
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void post_receive(void) {
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disable_irq(MACA);
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last_post = RX_POST;
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/* this sets the rxlen field */
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/* this is undocumented but very important */
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/* you will not receive anything without setting it */
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*MACA_TXLEN = (MAX_PACKET_SIZE << 16);
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if(dma_rx == 0) {
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dma_rx = get_free_packet();
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if (dma_rx == 0)
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printf("trying to fill MACA_DMARX but out of packet buffers\n");
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}
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*MACA_DMARX = (uint32_t)&(dma_rx->data[0]);
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/* with timeout */
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*MACA_SFTCLK = *MACA_CLK + RECV_SOFTIMEOUT; /* soft timeout */
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*MACA_TMREN = (1 << maca_tmren_sft);
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/* start the receive sequence */
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enable_irq(MACA);
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/* *MACA_CONTROL = ( (1 << maca_ctrl_asap) |
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(1 << maca_ctrl_auto) |
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(1 << maca_ctrl_prm) |
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(maca_ctrl_seq_rx));
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*/
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*MACA_CONTROL = (
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(1 << maca_ctrl_asap) |
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(1 << maca_ctrl_prm) |
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(maca_ctrl_seq_rx));
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}
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volatile packet_t* rx_packet(void) {
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volatile packet_t *p;
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safe_irq_disable(MACA);
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@ -110,14 +148,16 @@ volatile packet_t* rx_packet(void) {
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rx_head->right = 0;
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}
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print_packets("rx_packet");
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// print_packets("rx_packet");
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irq_restore();
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if(get_field(*MACA_STATUS,CODE) != NOT_COMPLETED) { post_receive(); }
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return p;
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}
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void post_tx(void) {
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/* set dma tx pointer to the payload */
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/* and set the tx len */
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disable_irq(MACA);
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last_post = TX_POST;
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dma_tx = tx_head;
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@ -154,7 +194,7 @@ void tx_packet(volatile packet_t *p) {
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/* move the queue */
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tx_end = p; tx_end->left = 0;
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}
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print_packets("tx packet");
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// print_packets("tx packet");
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irq_restore();
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if(get_field(*MACA_STATUS,CODE) != NOT_COMPLETED) { post_tx(); }
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return;
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@ -189,7 +229,7 @@ void free_tx_head(void) {
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if(tx_head == 0) { tx_end = 0; }
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free_packet(p);
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print_packets("free tx head");
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// print_packets("free tx head");
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irq_restore();
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return;
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}
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@ -209,46 +249,16 @@ void add_to_rx(volatile packet_t *p) {
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rx_end = p; rx_end->left = 0;
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}
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print_packets("add to tx");
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// print_packets("add to rx");
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irq_restore();
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return;
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}
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void post_receive(void) {
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disable_irq(MACA);
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last_post = RX_POST;
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/* this sets the rxlen field */
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/* this is undocumented but very important */
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/* you will not receive anything without setting it */
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*MACA_TXLEN = (MAX_PACKET_SIZE << 16);
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if(dma_rx == 0) {
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dma_rx = get_free_packet();
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if (dma_rx == 0)
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printf("trying to fill MACA_DMARX but out of packet buffers\n");
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}
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*MACA_DMARX = (uint32_t)&(dma_rx->data[0]);
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/* with timeout */
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*MACA_SFTCLK = *MACA_CLK + RECV_SOFTIMEOUT; /* soft timeout */
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*MACA_TMREN = (1 << maca_tmren_sft);
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/* start the receive sequence */
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enable_irq(MACA);
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/* *MACA_CONTROL = ( (1 << maca_ctrl_asap) |
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(1 << maca_ctrl_auto) |
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(1 << maca_ctrl_prm) |
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(maca_ctrl_seq_rx));
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*/
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*MACA_CONTROL = (
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(1 << maca_ctrl_asap) |
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(1 << maca_ctrl_prm) |
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(maca_ctrl_seq_rx));
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}
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void decode_status(volatile uint32_t status) {
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volatile uint32_t code;
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code = get_field(status,CODE);
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PRINTF("status code 0x%x\n\r",code);
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/* PRINTF("status code 0x%x\n\r",code); */
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switch(code)
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{
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@ -296,6 +306,7 @@ void decode_status(volatile uint32_t status) {
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case SUCCESS:
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{
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//PRINTF("maca: success\n\r");
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ResumeMACASync();
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break;
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}
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default:
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@ -310,7 +321,7 @@ void decode_status(volatile uint32_t status) {
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void maca_isr(void) {
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volatile uint32_t i, status;
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print_packets("maca_isr");
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// print_packets("maca_isr");
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status = *MACA_STATUS;
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@ -332,11 +343,12 @@ void maca_isr(void) {
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*MACA_CLRIRQ = (1 << maca_irq_crc);
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}
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if(action_complete_irq()) {
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PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE));
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/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
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if(last_post == TX_POST) {
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free_tx_head();
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last_post = NO_POST;
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}
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ResumeMACASync();
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*MACA_CLRIRQ = (1 << maca_irq_acpl);
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}
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i = *MACA_IRQ;
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@ -856,8 +868,8 @@ void ResumeMACASync(void)
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// bool_t tmpIsrStatus;
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volatile uint32_t i, saved_irq;
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disable_irq(MACA);
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saved_irq = *MACA_IRQ;
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// disable_irq(MACA);
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// saved_irq = *MACA_IRQ;
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// ITC_DisableInterrupt(gMacaInt_c);
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// AppInterrupts_ProtectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
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@ -905,7 +917,7 @@ void ResumeMACASync(void)
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// AppInterrupts_UnprotectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
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// ITC_EnableInterrupt(gMacaInt_c);
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*MACA_IRQ = saved_irq;
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enable_irq(MACA);
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// *MACA_IRQ = saved_irq;
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// enable_irq(MACA);
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}
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@ -47,7 +47,7 @@ uint32_t get_time(void) {
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#define random_short_addr() (*MACA_RANDOM & ones(sizeof(short_addr_t)*8))
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void build_session_req(volatile packet_t *p) {
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p->length = 4;
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p->length = 127;
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p->data[0] = 0xff;
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p->data[1] = 0x01;
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p->data[2] = 0x23;
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build_session_req(p);
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tx_packet(p);
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} else {
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printf("session_req: could not get free packet for transmit\n\r");
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// printf("session_req: could not get free packet for transmit\n\r");
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}
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// }
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/* generate a random short address */
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my_addr = random_short_addr();
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/* sets up tx_on, should be a board specific item */
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*GPIO_FUNC_SEL2 = (0x01 << ((44-16*2)*2));
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*GPIO_PAD_DIR0 = *GPIO_PAD_DIR0 | (1<<(44-32));
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state = SCANNING;
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while(1) {
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