progress on maca overhaul
This commit is contained in:
Mariano Alvira
parent
b92dec6ee8
commit
5bda57ed39
3 changed files with 535 additions and 235 deletions
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@ -1,15 +1,16 @@
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#ifndef _MACA_H_
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#define _MACA_H_
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#include <packet.h>
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#include <types.h>
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#include <utils.h>
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#define MACA_BASE ((volatile uint32_t *) 0x80004000)
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#define MACA_RESET ((volatile uint32_t *) 0x80004004)
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#define MACA_RANDOM ((volatile uint32_t *) 0x80004008)
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#define MACA_CONTROL ((volatile uint32_t *) 0x8000400c) /* write only, reads as 0 */
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#define MACA_BASE (0x80004000)
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#define MACA_RESET ((volatile uint32_t *) (MACA_BASE+0x04))
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#define MACA_RANDOM ((volatile uint32_t *) (MACA_BASE+0x08))
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#define MACA_CONTROL ((volatile uint32_t *) (MACA_BASE+0x0c))
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/* MACA_CONTROL bits and fields */
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#define ISM 20
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#define PRECOUNT 16 /* preamble reapeat counter */
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#define PRECOUNT_MASK bit_mask(4,PRECOUNT)
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@ -32,12 +33,78 @@
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#define SEQUENCE 0
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#define SEQUENCE_MASK bit_mask(3,SEQUENCE)
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/* end of MACA_CONTROL bits and fields */
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#define MACA_STATUS ((volatile uint32_t *) 0x80004010)
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#define MACA_DMARX ((volatile uint32_t *) 0x80004080)
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#define MACA_DMATX ((volatile uint32_t *) 0x80004084)
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#define MACA_GETRXLVL ((volatile uint32_t *) 0x80004098)
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#define MACA_PREAMBLE ((volatile uint32_t *) 0x8000411c)
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#define MACA_STATUS ((volatile uint32_t *) (MACA_BASE+0x10))
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/* MACA_STATUS bits and fields */
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#define STATUS_TIMEOUT 15
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#define CRC 14
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#define BUSY 13
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#define OVR 12
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#define CODE 0
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#define CODE_MASK bit_mask(4,CODE)
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/* status codes */
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#define SUCCESS 0
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#define CODE_TIMEOUT 1
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#define CHANNEL_BUSY 2
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#define CRC_FAILED 3
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#define ABORTED 4
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#define NO_ACK 5
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#define NO_DATA 6
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#define LATE_START 7
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#define EXT_TIMEOUT 8
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#define EXT_PND_TIMEOUT 9
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#define PLL_UNLOCK 12
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#define EXTERNAL_ABORT 13
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#define NOT_COMPLETED 14
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#define DMA_BUS_ERROR 15
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/* end of MACA_CONTROL bits and fields */
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#define MACA_FRMPND ((volatile uint32_t *) (MACA_BASE+0x14))
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#define MACA_TMREN ((volatile uint32_t *) (MACA_BASE+0x40))
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#define MACA_TMRDIS ((volatile uint32_t *) (MACA_BASE+0x44))
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#define MACA_CLK ((volatile uint32_t *) (MACA_BASE+0x48))
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#define MACA_STARTCLK ((volatile uint32_t *) (MACA_BASE+0x4c))
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#define MACA_CPLCLK ((volatile uint32_t *) (MACA_BASE+0x50))
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#define MACA_SFTCLK ((volatile uint32_t *) (MACA_BASE+0x54))
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#define MACA_CLKOFFSET ((volatile uint32_t *) (MACA_BASE+0x58))
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#define MACA_RELCLK ((volatile uint32_t *) (MACA_BASE+0x5c))
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#define MACA_CPLTIM ((volatile uint32_t *) (MACA_BASE+0x60))
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#define MACA_SLOTOFFSET ((volatile uint32_t *) (MACA_BASE+0x64))
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#define MACA_TIMESTAMP ((volatile uint32_t *) (MACA_BASE+0x68))
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#define MACA_DMARX ((volatile uint32_t *) (MACA_BASE+0x80))
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#define MACA_DMATX ((volatile uint32_t *) (MACA_BASE+0x84))
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#define MACA_DMAPOLL ((volatile uint32_t *) (MACA_BASE+0x88))
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#define MACA_TXLEN ((volatile uint32_t *) (MACA_BASE+0x8c))
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#define MACA_TXSEQNR ((volatile uint32_t *) (MACA_BASE+0x90))
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#define MACA_SETRXLVL ((volatile uint32_t *) (MACA_BASE+0x94))
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#define MACA_GETRXLVL ((volatile uint32_t *) (MACA_BASE+0x98))
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#define MACA_IRQ ((volatile uint32_t *) (MACA_BASE+0xc0))
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#define MACA_CLRIRQ ((volatile uint32_t *) (MACA_BASE+0xc4))
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#define MACA_SETIRQ ((volatile uint32_t *) (MACA_BASE+0xc8))
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#define MACA_MASKIRQ ((volatile uint32_t *) (MACA_BASE+0xcc))
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#define MACA_MACPANID ((volatile uint32_t *) (MACA_BASE+0x100))
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#define MACA_MAC16ADDR ((volatile uint32_t *) (MACA_BASE+0x104))
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#define MACA_MAC64HI ((volatile uint32_t *) (MACA_BASE+0x108))
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#define MACA_MAC64LO ((volatile uint32_t *) (MACA_BASE+0x10c))
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#define MACA_FLTREJ ((volatile uint32_t *) (MACA_BASE+0x110))
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#define MACA_CLKDIV ((volatile uint32_t *) (MACA_BASE+0x114))
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#define MACA_WARMUP ((volatile uint32_t *) (MACA_BASE+0x118))
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#define MACA_PREAMBLE ((volatile uint32_t *) (MACA_BASE+0x11c))
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#define MACA_WHITESEED ((volatile uint32_t *) (MACA_BASE+0x120))
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#define MACA_FRAMESYNC0 ((volatile uint32_t *) (MACA_BASE+0x124))
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#define MACA_FRAMESYNC1 ((volatile uint32_t *) (MACA_BASE+0x128))
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#define MACA_TXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x140))
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#define MACA_RXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x144))
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#define MACA_EOFDELAY ((volatile uint32_t *) (MACA_BASE+0x148))
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#define MACA_CCADELAY ((volatile uint32_t *) (MACA_BASE+0x14c))
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#define MACA_RXEND ((volatile uint32_t *) (MACA_BASE+0x150))
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#define MACA_TXCCADELAY ((volatile uint32_t *) (MACA_BASE+0x154))
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#define MACA_KEY3 ((volatile uint32_t *) (MACA_BASE+0x158))
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#define MACA_KEY2 ((volatile uint32_t *) (MACA_BASE+0x15c))
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#define MACA_KEY1 ((volatile uint32_t *) (MACA_BASE+0x160))
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#define MACA_KEY0 ((volatile uint32_t *) (MACA_BASE+0x164))
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#define MACA_OPTIONS ((volatile uint32_t *) (MACA_BASE+0x180))
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void reset_maca(void);
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void init_phy(void);
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@ -50,6 +117,12 @@ uint32_t init_from_flash(uint32_t addr);
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void set_power(uint8_t power);
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void set_channel(uint8_t chan);
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void tx_packet(volatile packet_t *p);
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volatile packet_t* rx_packet(void);
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volatile packet_t* get_free_packet(void);
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void free_packet(volatile packet_t *p);
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void free_all_packets(void);
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/******************************************************************************/
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/* everything under this comment is messy, needs cleaning, and will */
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/* probably change in the future */
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@ -113,143 +186,6 @@ enum {
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control_seq_cca = 6,
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control_seq_ed = 7
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};
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#define maca_status_cc_mask (0x0F)
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#define maca_reset_rst (1<<0)
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#define maca_reset_cln_on (1<<1)
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#define maca_frmpnd_data_pending (1<<0)
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#define maca_frmpnd_no_data_pending (0x00)
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#define maca_txlen_max_rxlen (127<<16)
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#define max_rx_ackwnd_slotted_mode (0xFFF<<16)
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#define max_rx_ackwnd_normal_mode (0xFFF)
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#define maca_irq_strt (1<<15) /*
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STRT
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Bit 15
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Action Started Interrupt—An auto-sequence is started, either
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immediately or by timer trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_sync (1<<14) /*
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SYNC
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Bit 14
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Sync Detected Interrupt—The modem has detected the beginning
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of a new packet
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_cm (1<<13) /*
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CM
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Bit 13
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Complete Clock Interrupt—The complete clock has generated a
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trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_crc (1<<12) /*
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CRC
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Bit 12
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Checksum Failed Interrupt—The checksum failed for the received
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packet.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_flt (1<<11) /*
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FLT
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Bit 11
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Filter Failed Interrupt—The receive header filter failed. 1 = Clear interrupt source
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0 = Leave source untouched
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SFT
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Bit 10
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Soft Complete Clock Interrupt—The soft complete clock has
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generated a trigger.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_sftclk (1<<10)
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#define maca_irq_lvl (1<<9) /*
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LVL
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Bit 9
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FIFO Level interrupt—The receive FIFO level is reached or
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exceeded.
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1 = Clear interrupt source
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0 = Leave source untouched
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Bit 8-5 Reserved bits—Read as zero and written with zero for future
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compatibility. N/A
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*/
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#define maca_irq_rst (1<<4) /*
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RST
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Bit 4
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Reset Interrupt—A non maskable reset interrupt detected (TBD!!!) 1 = Clear interrupt source
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0 = Leave source untouched
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WU
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Bit 3
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Wake-up Interrupt—Low power mode has been exited (TBD in
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connection with CCM module).
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_wu (1<<3)
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#define maca_irq_di (1<<2) /*
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DI
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Bit 2
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Data Indication Interrupt—During receive, a packet has been
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successfully received.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_poll (1<<1) /*
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POLL
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Bit 1
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Poll Indication Interrupt—Issued when data request received (and
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before ACK transmitted). MCU may then set MACA_FRMPND and
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prepare fast response. TBD: Shall this be skipped if
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MACA_FRMPND is clear?
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_irq_acpl (1<<0) /*
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ACPL
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Action Complete Interrupt—Marks the completion of a complete
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auto-sequence.
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1 = Clear interrupt source
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0 = Leave source untouched
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*/
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#define maca_start_clk (1<<0)/*
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TMREN & TMRDIS enable/disable start clock
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*/
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#define maca_cpl_clk (1<<1)/*
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TMREN & TMRDIS enable/disable complete clock
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*/
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#define maca_soft_clk (1<<2)/*
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TMREN & TMRDIS enable/disable soft complete clock
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*/
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#define maca_abort_start_clk (1<<3)/*
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TMRDIS abort start clock
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*/
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#define maca_abort_cpl_clk (1<<4)/*
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TMRDIS abort complete clock
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*/
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#define maca_abort_soft_clk (1<<5)/*
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TMRDIS abort soft complete clock
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*/
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#define maca_version (*((volatile uint32_t *)(0x80004000)))
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#define maca_reset (*((volatile uint32_t *)(0x80004004)))
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@ -378,24 +314,6 @@ typedef union maca_reset_reg_tag
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#define MACA_CTRL_MODE_NON_SLOTTED (1)
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#define MACA_CTRL_MODE_SLOTTED (2)
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typedef union maca_status_reg_tag
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{
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struct
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{
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uint32_t RESERVED:16;
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uint32_t TO:1;
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uint32_t CRC:1;
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uint32_t BUSY:1;
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uint32_t OVR:1;
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uint32_t zigbee:1;
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uint32_t :7;
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uint32_t COMPLETE_CODE:4;
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} Bits;
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uint32_t Reg;
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} maca_status_reg_t;
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typedef enum maca_freq_chann_tag
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{
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SMAC_CHANN_11 = 0,
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@ -418,32 +336,107 @@ typedef enum maca_freq_chann_tag
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} maca_freq_chann_t;
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typedef union maca_maskirq_reg_tag
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{
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struct
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{
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uint32_t RESERVED1:16;
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uint32_t STRT:1;
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uint32_t SYNC:1;
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uint32_t CM:1;
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uint32_t CRC:1;
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uint32_t FLT:1;
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uint32_t SFT:1;
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uint32_t LVL:1;
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uint32_t RESERVED0:4;
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uint32_t NOT_USED1:1;
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uint32_t NOT_USED0:1;
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uint32_t DI:1;
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uint32_t POLL:1;
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uint32_t ACPL:1;
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} Bits;
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uint32_t Reg;
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} maca_maskirq_reg_t;
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/* Sequence complete codes */
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enum maca_complete_code {
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maca_cc_success = 0,
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maca_cc_timeout = 1,
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maca_cc_channel_busy = 2,
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maca_cc_crc_fail = 3,
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maca_cc_aborted = 4,
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maca_cc_no_ack = 5,
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maca_cc_no_data = 6,
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maca_cc_late_start = 7,
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maca_cc_ext_timeout = 8,
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maca_cc_ext_pnd_timeout = 9,
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maca_cc_nc1 = 10,
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maca_cc_nc2 = 11,
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maca_cc_nc3 = 12,
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maca_cc_cc_external_abort= 13,
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maca_cc_not_completed = 14,
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maca_cc_bus_error = 15
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};
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/* control sequence codes */
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enum maca_ctrl_seq {
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maca_ctrl_seq_nop = 0,
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maca_ctrl_seq_abort = 1,
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maca_ctrl_seq_wait = 2,
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maca_ctrl_seq_tx = 3,
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maca_ctrl_seq_rx = 4,
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maca_ctrl_seq_txpoll = 5,
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maca_ctrl_seq_cca = 6,
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maca_ctrl_seq_ed = 7
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};
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#define _is_action_complete_interrupt(x) (0 != (maca_irq_acpl & x))
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#define _is_filter_failed_interrupt(x) (0 != (maca_irq_flt & x))
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#define _is_checksum_failed_interrupt(x) (0 != (maca_irq_crc & x))
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/* transmission modes */
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enum maca_ctrl_modes {
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maca_ctrl_mode_no_cca = 0,
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maca_ctrl_mode_non_slotted_csma_ca = 1,
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maca_ctrl_mode_slotted_csma_ca = 2,
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};
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/* MACA_CONTROL bits */
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enum maca_ctrl_bits {
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maca_ctrl_seq = 0, /* 3 bits */
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maca_ctrl_mode = 3, /* 2 bits */
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maca_ctrl_tm = 5,
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maca_ctrl_lfsr = 6,
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maca_ctrl_auto = 7,
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maca_ctrl_bcn = 8,
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maca_ctrl_asap = 9,
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maca_ctrl_rel = 10,
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maca_ctrl_prm = 11,
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maca_ctrl_nofc = 12,
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maca_ctrl_role = 13,
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/* 14 reserved */
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maca_ctrl_rsto = 15,
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maca_ctrl_pre_count = 16, /* 4 bits */
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maca_ctrl_ism = 20,
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};
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/* MACA_IRQ bits */
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enum maca_irqs {
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maca_irq_acpl = 0,
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maca_irq_poll = 1,
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maca_irq_di = 2,
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maca_irq_wu = 3,
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maca_irq_rst = 4,
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maca_irq_lvl = 9,
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maca_irq_sftclk = 10,
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maca_irq_flt = 11,
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maca_irq_crc = 12,
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maca_irq_cm = 13,
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maca_irq_sync = 14,
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maca_irq_strt = 15,
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};
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/* MACA_RESET bits */
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enum maca_reset_bits {
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maca_reset_rst = 0,
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maca_reset_clkon = 1,
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};
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/* MACA_TMREN bits */
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enum maca_tmren_bits {
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maca_tmren_strt = 0,
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maca_tmren_cpl = 1,
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maca_tmren_sft = 2,
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};
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enum maca_status_bits {
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maca_status_ovr = 12,
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maca_status_busy = 13,
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maca_status_crc = 14,
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maca_status_to = 15,
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};
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#define action_complete_irq() bit_is_set(*MACA_IRQ,maca_irq_acpl)
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#define filter_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_flt)
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#define checksum_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_crc)
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#define data_indication_irq() bit_is_set(*MACA_IRQ,maca_irq_di)
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#define status_is_not_completed() ((*MACA_STATUS & 0xffff) == maca_cc_not_completed)
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#define status_is_success() ((*MACA_STATUS & 0xffff) == maca_cc_success)
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#define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted )
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