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Hardware/software radio HAL patch from Roger Larsson.

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Use CHANNEL_802_15_4 define for RF channel on all AVR platforms, default 26.
Remove hopefully unnecessary interrupt disable wrapper on eeprom reads and writes.
This commit is contained in:
dak664 2010-12-03 20:42:01 +00:00
parent 21b10e8021
commit 58b7a19803
12 changed files with 304 additions and 122 deletions
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120
cpu/avr/radio/rf230bb/hal.h
View file

@ -47,7 +47,7 @@
* \file * \file
* \brief This file contains low-level radio driver code. * \brief This file contains low-level radio driver code.
* *
* $Id: hal.h,v 1.4 2010/11/30 19:47:40 dak664 Exp $ * $Id: hal.h,v 1.5 2010/12/03 20:42:01 dak664 Exp $
*/ */
#ifndef HAL_AVR_H #ifndef HAL_AVR_H
@ -55,9 +55,7 @@
/*============================ INCLUDE =======================================*/ /*============================ INCLUDE =======================================*/
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <avr/io.h> //#include <util/crc16.h>
#include <avr/interrupt.h>
#include <util/crc16.h>
#include "contiki-conf.h" #include "contiki-conf.h"
/*============================ MACROS ========================================*/ /*============================ MACROS ========================================*/
@ -82,7 +80,7 @@
/* TODO: Move to platform (or CPU specific) */
#if RCB_REVISION == RCB_B #if RCB_REVISION == RCB_B
/* 1281 rcb */ /* 1281 rcb */
# define SSPORT B # define SSPORT B
@ -168,12 +166,49 @@
# define HAS_CW_MODE # define HAS_CW_MODE
# define HAS_SPARE_TIMER # define HAS_SPARE_TIMER
#elif CONTIKI_TARGET_MULLE
/* mulle 5.2 (TODO: move to platform specific) */
# define SSPORT 3
# define SSPIN 5
# define MOSIPORT 1
# define MOSIPIN 1
# define MISOPORT 1
# define MISOPIN 0
# define SCKPORT 3
# define SCKPIN 3
# define RSTPORT 4
# define RSTPIN 3
# define IRQPORT 8
# define IRQPIN 3
# define SLPTRPORT 0
# define SLPTRPIN 7
# define HAS_SPARE_TIMER
#else #else
#error "Platform undefined in hal.h" #error "Platform undefined in hal.h"
#endif #endif
/* For architectures that have all SPI signals on the same port */
#ifndef SSPORT
#define SSPORT SPIPORT
#endif
#ifndef SCKPORT
#define SCKPORT SPIPORT
#endif
#ifndef MOSIPORT
#define MOSIPORT SPIPORT
#endif
#ifndef MISOPORT
#define MISOPORT SPIPORT
#endif
/** \} */ /** \} */
/** /**
@ -185,6 +220,7 @@
* if TICKTIMER is defined as 0. * if TICKTIMER is defined as 0.
* \{ * \{
*/ */
#if defined(__AVR__)
#define CAT(x, y) x##y #define CAT(x, y) x##y
#define CAT2(x, y, z) x##y##z #define CAT2(x, y, z) x##y##z
#define DDR(x) CAT(DDR, x) #define DDR(x) CAT(DDR, x)
@ -212,6 +248,39 @@
#define COMPVECT(x) CAT2(TIMER,x,_COMPA_vect) #define COMPVECT(x) CAT2(TIMER,x,_COMPA_vect)
#define UDREVECT(x) CAT2(USART,x,_UDRE_vect) #define UDREVECT(x) CAT2(USART,x,_UDRE_vect)
#define RXVECT(x) CAT2(USART,x,_RX_vect) #define RXVECT(x) CAT2(USART,x,_RX_vect)
#endif
/* TODO: Move to CPU specific */
#if defined(CONTIKI_TARGET_MULLE)
#define CAT(x, y) x##y.BYTE
#define CAT2(x, y, z) x##y##z.BYTE
#define DDR(x) CAT(PD, x)
#define PORT(x) CAT(P, x)
#define PIN(x) CAT(P, x)
#define UCSR(num, let) CAT2(UCSR,num,let)
#define RXEN(x) CAT(RXEN,x)
#define TXEN(x) CAT(TXEN,x)
#define TXC(x) CAT(TXC,x)
#define RXC(x) CAT(RXC,x)
#define RXCIE(x) CAT(RXCIE,x)
#define UCSZ(x,y) CAT2(UCSZ,x,y)
#define UBRR(x,y) CAT2(UBRR,x,y)
#define UDRE(x) CAT(UDRE,x)
#define UDRIE(x) CAT(UDRIE,x)
#define UDR(x) CAT(UDR,x)
#define TCNT(x) CAT(TCNT,x)
#define TIMSK(x) CAT(TIMSK,x)
#define TCCR(x,y) CAT2(TCCR,x,y)
#define COM(x,y) CAT2(COM,x,y)
#define OCR(x,y) CAT2(OCR,x,y)
#define CS(x,y) CAT2(CS,x,y)
#define WGM(x,y) CAT2(WGM,x,y)
#define OCIE(x,y) CAT2(OCIE,x,y)
#define COMPVECT(x) CAT2(TIMER,x,_COMPA_vect)
#define UDREVECT(x) CAT2(USART,x,_UDRE_vect)
#define RXVECT(x) CAT2(USART,x,_RX_vect)
#endif
/** \} */ /** \} */
/** /**
@ -230,13 +299,24 @@
#define RST RSTPIN /**< Pin number that corresponds to the RST pin. */ #define RST RSTPIN /**< Pin number that corresponds to the RST pin. */
#define DDR_RST DDR( RSTPORT ) /**< Data Direction Register that corresponds to the port where RST is */ #define DDR_RST DDR( RSTPORT ) /**< Data Direction Register that corresponds to the port where RST is */
#define PORT_RST PORT( RSTPORT ) /**< Port (Write Access) where RST is connected. */ #define PORT_RST PORT( RSTPORT ) /**< Port (Write Access) where RST is connected. */
#define PIN_RST PIN( RSTPORT ) /**< Pin (Read Access) where RST is connected. */ #define PIN_RST PIN( RSTPORT /* BUG? */) /**< Pin (Read Access) where RST is connected. */
#define hal_set_rst_high( ) ( PORT_RST |= ( 1 << RST ) ) /**< This macro pulls the RST pin high. */ #define hal_set_rst_high( ) ( PORT_RST |= ( 1 << RST ) ) /**< This macro pulls the RST pin high. */
#define hal_set_rst_low( ) ( PORT_RST &= ~( 1 << RST ) ) /**< This macro pulls the RST pin low. */ #define hal_set_rst_low( ) ( PORT_RST &= ~( 1 << RST ) ) /**< This macro pulls the RST pin low. */
#define hal_get_rst( ) ( ( PIN_RST & ( 1 << RST ) ) >> RST ) /**< Read current state of the RST pin (High/Low). */ #define hal_get_rst( ) ( ( PIN_RST & ( 1 << RST ) ) >> RST ) /**< Read current state of the RST pin (High/Low). */
#define HAL_SS_PIN SSPIN /**< The slave select pin. */ #define HAL_SS_PIN SSPIN /**< The slave select pin. */
#define HAL_SCK_PIN SCKPIN /**< Data bit for SCK. */
#define HAL_MOSI_PIN MOSIPIN
#define HAL_MISO_PIN MISOPIN
#define HAL_PORT_SPI PORT( SPIPORT ) /**< The SPI module is located on PORTB. */ #define HAL_PORT_SPI PORT( SPIPORT ) /**< The SPI module is located on PORTB. */
#define HAL_PORT_SS PORT( SSPORT )
#define HAL_PORT_SCK PORT( SCKPORT )
#define HAL_PORT_MOSI PORT( MOSIPORT ) /**< The SPI module uses GPIO might be split on different ports. */
#define HAL_PORT_MISO PORT( MISOPORT ) /**< The SPI module uses GPIO might be split on different ports. */
#define HAL_DDR_SPI DDR( SPIPORT ) /**< Data Direction Register for PORTB. */ #define HAL_DDR_SPI DDR( SPIPORT ) /**< Data Direction Register for PORTB. */
#define HAL_DDR_SS DDR( SSPORT ) /**< Data Direction Register for MISO GPIO pin. */
#define HAL_DDR_SCK DDR( SCKPORT ) /**< Data Direction Register for MISO GPIO pin. */
#define HAL_DDR_MOSI DDR( MOSIPORT ) /**< Data Direction Register for MISO GPIO pin. */
#define HAL_DDR_MISO DDR( MISOPORT ) /**< Data Direction Register for MOSI GPIO pin. */
#define HAL_DD_SS SSPIN /**< Data Direction bit for SS. */ #define HAL_DD_SS SSPIN /**< Data Direction bit for SS. */
#define HAL_DD_SCK SCKPIN /**< Data Direction bit for SCK. */ #define HAL_DD_SCK SCKPIN /**< Data Direction bit for SCK. */
#define HAL_DD_MOSI MOSIPIN /**< Data Direction bit for MOSI. */ #define HAL_DD_MOSI MOSIPIN /**< Data Direction bit for MOSI. */
@ -244,8 +324,8 @@
/** \} */ /** \} */
#define HAL_SS_HIGH( ) (HAL_PORT_SPI |= ( 1 << HAL_SS_PIN )) /**< MACRO for pulling SS high. */ #define HAL_SS_HIGH( ) (HAL_PORT_SS |= ( 1 << HAL_SS_PIN )) /**< MACRO for pulling SS high. */
#define HAL_SS_LOW( ) (HAL_PORT_SPI &= ~( 1 << HAL_SS_PIN )) /**< MACRO for pulling SS low. */ #define HAL_SS_LOW( ) (HAL_PORT_SS &= ~( 1 << HAL_SS_PIN )) /**< MACRO for pulling SS low. */
/** \brief Macros defined for HAL_TIMER1. /** \brief Macros defined for HAL_TIMER1.
* *
@ -254,6 +334,7 @@
* symbols (16 us ticks). * symbols (16 us ticks).
*/ */
#if defined(__AVR__)
#if ( F_CPU == 16000000UL ) #if ( F_CPU == 16000000UL )
#define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS12 ) ) #define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS12 ) )
#define HAL_US_PER_SYMBOL ( 1 ) #define HAL_US_PER_SYMBOL ( 1 )
@ -290,11 +371,28 @@
#define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 &= ~( 1 << TOIE1 ) ) #define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 &= ~( 1 << TOIE1 ) )
/** This macro will protect the following code from interrupts.*/ /** This macro will protect the following code from interrupts.*/
#define AVR_ENTER_CRITICAL_REGION( ) {uint8_t volatile saved_sreg = SREG; cli( ) #define HAL_ENTER_CRITICAL_REGION( ) {uint8_t volatile saved_sreg = SREG; cli( )
/** This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION /** This macro must always be used in conjunction with HAL_ENTER_CRITICAL_REGION
so that interrupts are enabled again.*/ so that interrupts are enabled again.*/
#define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;} #define HAL_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;}
#else /* MULLE */
#define HAL_ENABLE_RADIO_INTERRUPT( ) ( INT1IC.BYTE |= 1 )
#define HAL_DISABLE_RADIO_INTERRUPT( ) ( INT1IC.BYTE &= ~(1) )
#define HAL_ENABLE_OVERFLOW_INTERRUPT( ) ( TB4IC.BYTE = 1 )
#define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TB4IC.BYTE = 0 )
/** This macro will protect the following code from interrupts.*/
#define HAL_ENTER_CRITICAL_REGION( ) MULLE_ENTER_CRITICAL_REGION( )
/** This macro must always be used in conjunction with HAL_ENTER_CRITICAL_REGION
so that interrupts are enabled again.*/
#define HAL_LEAVE_CRITICAL_REGION( ) MULLE_LEAVE_CRITICAL_REGION( )
#endif /* !__AVR__ */
/** \brief Enable the interrupt from the radio transceiver. /** \brief Enable the interrupt from the radio transceiver.

221
cpu/avr/radio/rf230bb/halbb.c
View file

@ -132,44 +132,74 @@ static uint16_t hal_system_time = 0;
/*============================ PROTOTYPES ====================================*/ /*============================ PROTOTYPES ====================================*/
/*============================ IMPLEMENTATION ================================*/ /*============================ IMPLEMENTATION ================================*/
#ifndef RF230BB_HARDWARE_SPI #if defined(__AVR__)
#define RF230BB_HARDWARE_SPI 1 /*
#endif * AVR with hardware SPI tranfers (TODO: move to hw spi hal for avr cpu)
*/
#include <avr/io.h>
#include <avr/interrupt.h>
#if RF230BB_HARDWARE_SPI
// AVR with hardware spi tranfers
#define HAL_SPI_TRANSFER_OPEN() { \ #define HAL_SPI_TRANSFER_OPEN() { \
AVR_ENTER_CRITICAL_REGION(); \ HAL_ENTER_CRITICAL_REGION(); \
HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */ HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */
#define HAL_SPI_TRANSFER_WRITE(to_write) SPDR = to_write #define HAL_SPI_TRANSFER_WRITE(to_write) (SPDR = (to_write))
#define HAL_SPI_TRANSFER_WAIT() ({while ((SPSR & (1 << SPIF)) == 0) {;}}) /* gcc extension, alternative inline function */ #define HAL_SPI_TRANSFER_WAIT() ({while ((SPSR & (1 << SPIF)) == 0) {;}}) /* gcc extension, alternative inline function */
#define HAL_SPI_TRANSFER_READ() (SPDR) #define HAL_SPI_TRANSFER_READ() (SPDR)
#define HAL_SPI_TRANSFER_CLOSE() \ #define HAL_SPI_TRANSFER_CLOSE() \
HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \ HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \
AVR_LEAVE_CRITICAL_REGION(); \ HAL_LEAVE_CRITICAL_REGION(); \
} }
#define HAL_SPI_TRANSFER(to_write) ( \ #define HAL_SPI_TRANSFER(to_write) ( \
HAL_SPI_TRANSFER_WRITE(to_write), \ HAL_SPI_TRANSFER_WRITE(to_write), \
HAL_SPI_TRANSFER_WAIT(), \ HAL_SPI_TRANSFER_WAIT(), \
HAL_SPI_TRANSFER_READ() ) HAL_SPI_TRANSFER_READ() )
#else /* RF230BB_HARDWARE_SPI */ #else /* __AVR__ */
// Software SPI transfers (Mulle, for reference) /*
* Other SPI architecture (parts to core, parts to m16c6Xp
*/
#include "contiki-mulle.h" // MULLE_ENTER_CRITICAL_REGION
// Software SPI transfers
#define HAL_SPI_TRANSFER_OPEN() { uint8_t spiTemp; \ #define HAL_SPI_TRANSFER_OPEN() { uint8_t spiTemp; \
AVR_ENTER_CRITICAL_REGION(); \ HAL_ENTER_CRITICAL_REGION(); \
HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */ HAL_SS_LOW(); /* Start the SPI transaction by pulling the Slave Select low. */
#define HAL_SPI_TRANSFER_WRITE(to_write) (spiTemp = spiWrite(to_write)) #define HAL_SPI_TRANSFER_WRITE(to_write) (spiTemp = spiWrite(to_write))
#define HAL_SPI_TRANSFER_WAIT() (0) #define HAL_SPI_TRANSFER_WAIT() ({0;})
#define HAL_SPI_TRANSFER_READ() (spiTemp) #define HAL_SPI_TRANSFER_READ() (spiTemp)
#define HAL_SPI_TRANSFER_CLOSE() \ #define HAL_SPI_TRANSFER_CLOSE() \
HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \ HAL_SS_HIGH(); /* End the transaction by pulling the Slave Select High. */ \
AVR_LEAVE_CRITICAL_REGION(); \ HAL_LEAVE_CRITICAL_REGION(); \
} }
#define HAL_SPI_TRANSFER(to_write) (spiTemp = spiWrite(to_write)) #define HAL_SPI_TRANSFER(to_write) (spiTemp = spiWrite(to_write))
#endif /* RF230BB_HARDWARE_SPI */
inline uint8_t spiWrite(uint8_t byte)
{
uint8_t data = 0;
uint8_t mask = 0x80;
do
{
if( (byte & mask) != 0 )
HAL_PORT_MOSI |= (1 << HAL_MOSI_PIN); //call MOSI.set();
else
HAL_PORT_MOSI &= ~(1 << HAL_MOSI_PIN); //call MOSI.clr();
HAL_PORT_SCK &= ~(1 << HAL_SCK_PIN); //call SCLK.clr();
if( (HAL_PORT_MISO & (1 << HAL_MISO_PIN)) > 0) //call MISO.get() )
data |= mask;
HAL_PORT_SCK |= (1 << HAL_SCK_PIN); //call SCLK.set();
} while( (mask >>= 1) != 0 );
return data;
}
#endif /* !__AVR__ */
/** \brief This function initializes the Hardware Abstraction Layer. /** \brief This function initializes the Hardware Abstraction Layer.
*/ */
#if defined(__AVR__)
#define HAL_RF230_ISR() ISR(RADIO_VECT)
#define HAL_TIME_ISR() ISR(TIMER1_OVF_vect)
#define HAL_TICK_UPCNT() (TCNT1)
void void
hal_init(void) hal_init(void)
{ {
@ -177,7 +207,7 @@ hal_init(void)
hal_system_time = 0; hal_system_time = 0;
// hal_reset_flags(); // hal_reset_flags();
/*IO Specific Initialization.*/ /*IO Specific Initialization - sleep and reset pins. */
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */ DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RST); /* Enable RST as output. */ DDR_RST |= (1 << RST); /* Enable RST as output. */
@ -196,6 +226,49 @@ hal_init(void)
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */ hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
} }
#else /* __AVR__ */
#define HAL_RF230_ISR() M16C_INTERRUPT(M16C_INT1)
#define HAL_TIME_ISR() M16C_INTERRUPT(M16C_TMRB4)
#define HAL_TICK_UPCNT() (0xFFFF-TB4) // TB4 counts down so we need to convert it to upcounting
void
hal_init(void)
{
/*Reset variables used in file.*/
hal_system_time = 0;
// hal_reset_flags();
/*IO Specific Initialization - sleep and reset pins. */
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RST); /* Enable RST as output. */
/*SPI Specific Initialization.*/
/* Set SS, CLK and MOSI as output. */
HAL_DDR_SS |= (1 << HAL_SS_PIN);
HAL_DDR_SCK |= (1 << HAL_SCK_PIN);
HAL_DDR_MOSI |= (1 << HAL_MOSI_PIN);
HAL_DDR_MISO &= ~(1 << HAL_MISO_PIN);
/* Set SS */
HAL_PORT_SS |= (1 << HAL_SS_PIN); // HAL_SS_HIGH()
HAL_PORT_SCK |= (1 << HAL_SCK_PIN);
/*TIMER Specific Initialization.*/
// Init count source (Timer B3)
TB3 = ((16*10) - 1); // 16 us ticks
TB3MR.BYTE = 0b00000000; // Timer mode, F1
TBSR.BIT.TB3S = 1; // Start Timer B3
TB4 = 0xFFFF; //
TB4MR.BYTE = 0b10000001; // Counter mode, count TB3
TBSR.BIT.TB4S = 1; // Start Timer B4
INT1IC.BIT.POL = 1; // Select rising edge
HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer overflow interrupt. */
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
}
#endif /* !__AVR__ */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/** \brief This function reset the interrupt flags and interrupt event handlers /** \brief This function reset the interrupt flags and interrupt event handlers
* (Callbacks) to their default value. * (Callbacks) to their default value.
@ -203,7 +276,7 @@ hal_init(void)
//void //void
//hal_reset_flags(void) //hal_reset_flags(void)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
/* Reset Flags. */ /* Reset Flags. */
// hal_bat_low_flag = 0; // hal_bat_low_flag = 0;
@ -213,7 +286,7 @@ hal_init(void)
// rx_start_callback = NULL; // rx_start_callback = NULL;
// trx_end_callback = NULL; // trx_end_callback = NULL;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -235,9 +308,9 @@ hal_init(void)
//void //void
//hal_clear_bat_low_flag(void) //hal_clear_bat_low_flag(void)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// hal_bat_low_flag = 0; // hal_bat_low_flag = 0;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -257,9 +330,9 @@ hal_init(void)
//void //void
//hal_set_trx_end_event_handler(hal_trx_end_isr_event_handler_t trx_end_callback_handle) //hal_set_trx_end_event_handler(hal_trx_end_isr_event_handler_t trx_end_callback_handle)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// trx_end_callback = trx_end_callback_handle; // trx_end_callback = trx_end_callback_handle;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -268,9 +341,9 @@ hal_init(void)
//void //void
//hal_clear_trx_end_event_handler(void) //hal_clear_trx_end_event_handler(void)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// trx_end_callback = NULL; // trx_end_callback = NULL;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -291,9 +364,9 @@ hal_init(void)
//void //void
//hal_set_rx_start_event_handler(hal_rx_start_isr_event_handler_t rx_start_callback_handle) //hal_set_rx_start_event_handler(hal_rx_start_isr_event_handler_t rx_start_callback_handle)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// rx_start_callback = rx_start_callback_handle; // rx_start_callback = rx_start_callback_handle;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -302,9 +375,9 @@ hal_init(void)
//void //void
//hal_clear_rx_start_event_handler(void) //hal_clear_rx_start_event_handler(void)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// rx_start_callback = NULL; // rx_start_callback = NULL;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -326,9 +399,9 @@ hal_init(void)
//void //void
//hal_clear_pll_lock_flag(void) //hal_clear_pll_lock_flag(void)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_ENTER_CRITICAL_REGION();
// hal_pll_lock_flag = 0; // hal_pll_lock_flag = 0;
// AVR_LEAVE_CRITICAL_REGION(); // HAL_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -488,7 +561,6 @@ hal_frame_read(hal_rx_frame_t *rx_frame)
do{ do{
*rx_data++ = HAL_SPI_TRANSFER_READ(); *rx_data++ = HAL_SPI_TRANSFER_READ();
HAL_SPI_TRANSFER_WRITE(0); HAL_SPI_TRANSFER_WRITE(0);
HAL_SPI_TRANSFER_WAIT();
// if (rx_frame){ // if (rx_frame){
// *rx_data++ = tempData; // *rx_data++ = tempData;
@ -500,13 +572,15 @@ hal_frame_read(hal_rx_frame_t *rx_frame)
/* A full buffer should be read in 320us at 2x spi clocking, so with a low interrupt latency overwrites should not occur */ /* A full buffer should be read in 320us at 2x spi clocking, so with a low interrupt latency overwrites should not occur */
// crc = _crc_ccitt_update(crc, tempData); // crc = _crc_ccitt_update(crc, tempData);
HAL_SPI_TRANSFER_WAIT();
} while (--frame_length > 0); } while (--frame_length > 0);
/*Read LQI value for this frame.*/ /*Read LQI value for this frame.*/
// if (rx_frame){ // if (rx_frame){
rx_frame->lqi = HAL_SPI_TRANSFER_READ(); rx_frame->lqi = HAL_SPI_TRANSFER_READ();
// } else { // } else {
// rx_callback(SPDR); // rx_callback(HAL_SPI_TRANSFER_READ());
// } // }
@ -567,31 +641,21 @@ hal_frame_write(uint8_t *write_buffer, uint8_t length)
//void //void
//hal_sram_read(uint8_t address, uint8_t length, uint8_t *data) //hal_sram_read(uint8_t address, uint8_t length, uint8_t *data)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_SPI_TRANSFER_OPEN();
// HAL_SS_LOW(); /* Initiate the SPI transaction. */
/*Send SRAM read command.*/ /*Send SRAM read command.*/
// SPDR = HAL_TRX_CMD_SR; // uint8_t dummy_read = HAL_SPI_TRANSFER(HAL_TRX_CMD_SR);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// uint8_t dummy_read = SPDR;
/*Send address where to start reading.*/ /*Send address where to start reading.*/
// SPDR = address; // dummy_read = HAL_SPI_TRANSFER(address);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// dummy_read = SPDR;
/*Upload the chosen memory area.*/ /*Upload the chosen memory area.*/
// do{ // do{
// SPDR = HAL_DUMMY_READ; // *data++ = HAL_SPI_TRANSFER(HAL_DUMMY_READ);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// *data++ = SPDR;
// } while (--length > 0); // } while (--length > 0);
// HAL_SS_HIGH(); // HAL_SPI_TRANSFER_CLOSE();
// AVR_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -606,30 +670,21 @@ hal_frame_write(uint8_t *write_buffer, uint8_t length)
//void //void
//hal_sram_write(uint8_t address, uint8_t length, uint8_t *data) //hal_sram_write(uint8_t address, uint8_t length, uint8_t *data)
//{ //{
// AVR_ENTER_CRITICAL_REGION(); // HAL_SPI_TRANSFER_OPEN();
// HAL_SS_LOW();
/*Send SRAM write command.*/ /*Send SRAM write command.*/
// SPDR = HAL_TRX_CMD_SW; // uint8_t dummy_read = HAL_SPI_TRANSFER(HAL_TRX_CMD_SW);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// uint8_t dummy_read = SPDR;
/*Send address where to start writing to.*/ /*Send address where to start writing to.*/
// SPDR = address; // dummy_read = HAL_SPI_TRANSFER(address);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// dummy_read = SPDR;
/*Upload the chosen memory area.*/ /*Upload the chosen memory area.*/
// do{ // do{
// SPDR = *data++; // dummy_read = HAL_SPI_TRANSFER(*data++);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// dummy_read = SPDR;
// } while (--length > 0); // } while (--length > 0);
// HAL_SS_HIGH(); // HAL_SPI_TRANSFER_CLOSE();
// AVR_LEAVE_CRITICAL_REGION();
//} //}
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
@ -654,24 +709,29 @@ volatile char rf230interruptflag;
#define INTERRUPTDEBUG(arg) #define INTERRUPTDEBUG(arg)
#endif #endif
ISR(RADIO_VECT) HAL_RF230_ISR()
{ {
/*The following code reads the current system time. This is done by first /*The following code reads the current system time. This is done by first
reading the hal_system_time and then adding the 16 LSB directly from the reading the hal_system_time and then adding the 16 LSB directly from the
TCNT1 register. Not implented in RF230BB for speed hardware counter.
*/ */
// uint32_t isr_timestamp = hal_system_time; // uint32_t isr_timestamp = hal_system_time;
// isr_timestamp <<= 16; // isr_timestamp <<= 16;
// isr_timestamp |= TCNT1; // isr_timestamp |= HAL_TICK_UPCNT(); // TODO: what if this wraps after reading hal_system_time?
volatile uint8_t state; volatile uint8_t state;
uint8_t interrupt_source; /* used after HAL_SPI_TRANSFER_OPEN/CLOSE block */
INTERRUPTDEBUG(1); INTERRUPTDEBUG(1);
/* Using SPI bus from ISR is generally a bad idea... */
/* Note: all IRQ are not always automatically disabled when running in ISR */
HAL_SPI_TRANSFER_OPEN();
/*Read Interrupt source.*/ /*Read Interrupt source.*/
HAL_SS_LOW();
/*Send Register address and read register content.*/ /*Send Register address and read register content.*/
SPDR = RG_IRQ_STATUS | HAL_TRX_CMD_RR; HAL_SPI_TRANSFER_WRITE(RG_IRQ_STATUS | HAL_TRX_CMD_RR);
/* This is the second part of the convertion of system time to a 16 us time /* This is the second part of the convertion of system time to a 16 us time
base. The division is moved here so we can spend less time waiting for SPI base. The division is moved here so we can spend less time waiting for SPI
@ -680,31 +740,26 @@ ISR(RADIO_VECT)
// isr_timestamp /= HAL_US_PER_SYMBOL; /* Divide so that we get time in 16us resolution. */ // isr_timestamp /= HAL_US_PER_SYMBOL; /* Divide so that we get time in 16us resolution. */
// isr_timestamp &= HAL_SYMBOL_MASK; // isr_timestamp &= HAL_SYMBOL_MASK;
while ((SPSR & (1 << SPIF)) == 0) {;} HAL_SPI_TRANSFER_WAIT(); /* AFTER possible interleaved processing */
uint8_t interrupt_source = SPDR; /* The interrupt variable is used as a dummy read. */
SPDR = interrupt_source; interrupt_source = HAL_SPI_TRANSFER_READ(); /* The interrupt variable is used as a dummy read. */
while ((SPSR & (1 << SPIF)) == 0) {;}
interrupt_source = SPDR; /* The interrupt source is read. */ interrupt_source = HAL_SPI_TRANSFER(interrupt_source);
HAL_SPI_TRANSFER_CLOSE();
HAL_SS_HIGH();
/*Handle the incomming interrupt. Prioritized.*/ /*Handle the incomming interrupt. Prioritized.*/
if ((interrupt_source & HAL_RX_START_MASK)){ if ((interrupt_source & HAL_RX_START_MASK)){
INTERRUPTDEBUG(10); INTERRUPTDEBUG(10);
// if(rx_start_callback != NULL){ // if(rx_start_callback != NULL){
// /* Read Frame length and call rx_start callback. */ // /* Read Frame length and call rx_start callback. */
// HAL_SS_LOW(); // HAL_SPI_TRANSFER_OPEN();
// SPDR = HAL_TRX_CMD_FR; // uint8_t frame_length = HAL_SPI_TRANSFER(HAL_TRX_CMD_FR);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// uint8_t frame_length = SPDR;
// SPDR = frame_length; /* frame_length used for dummy data */ // frame_length = HAL_SPI_TRANSFER(frame_length);
// while ((SPSR & (1 << SPIF)) == 0) {;}
// frame_length = SPDR;
// HAL_SS_HIGH(); // HAL_SPI_TRANSFER_CLOSE();
// rx_start_callback(isr_timestamp, frame_length); // rx_start_callback(isr_timestamp, frame_length);
// } // }
@ -728,10 +783,8 @@ ISR(RADIO_VECT)
#if RF230_CONF_AUTOACK #if RF230_CONF_AUTOACK
rf230_last_rssi=hal_subregister_read(SR_ED_LEVEL); rf230_last_rssi=hal_subregister_read(SR_ED_LEVEL);
if (rf230_last_rssi >= RF230_MIN_RX_POWER) { if (rf230_last_rssi >= RF230_MIN_RX_POWER) {
// if (hal_subregister_read(SR_ED_LEVEL) >= RF230_MIN_RX_POWER) {
#else #else
rf230_last_rssi=hal_subregister_read(SR_RSSI); rf230_last_rssi=hal_subregister_read(SR_RSSI);
// if (hal_subregister_read(SR_RSSI) >= RF230_MIN_RX_POWER/3) {
if (rf230_last_rssi >= RF230_MIN_RX_POWER/3) { if (rf230_last_rssi >= RF230_MIN_RX_POWER/3) {
#endif #endif
#endif #endif
@ -789,7 +842,7 @@ ISR(RADIO_VECT)
*/ */
void TIMER1_OVF_vect(void); void TIMER1_OVF_vect(void);
#else /* !DOXYGEN */ #else /* !DOXYGEN */
ISR(TIMER1_OVF_vect) HAL_TIME_ISR()
{ {
hal_system_time++; hal_system_time++;
} }

3
cpu/avr/radio/rf230bb/rf230bb.c
View file

@ -28,7 +28,7 @@
* *
* This file is part of the Contiki operating system. * This file is part of the Contiki operating system.
* *
* @(#)$Id: rf230bb.c,v 1.14 2010/11/26 20:39:15 dak664 Exp $ * @(#)$Id: rf230bb.c,v 1.15 2010/12/03 20:42:01 dak664 Exp $
*/ */
/* /*
* This code is almost device independent and should be easy to port. * This code is almost device independent and should be easy to port.
@ -43,6 +43,7 @@
#if defined(__AVR__) #if defined(__AVR__)
#include <avr/io.h> #include <avr/io.h>
#include <util/delay.h> #include <util/delay.h>
#define delay_us( us ) ( _delay_us( ( us ) ) )
#include <avr/pgmspace.h> #include <avr/pgmspace.h>
#elif defined(__MSP430__) #elif defined(__MSP430__)
#include <io.h> #include <io.h>

4
cpu/avr/radio/rf230bb/rf230bb.h
View file

@ -45,7 +45,7 @@
* \file * \file
* \brief This file contains radio driver code. * \brief This file contains radio driver code.
* *
* $Id: rf230bb.h,v 1.3 2010/09/17 21:59:09 dak664 Exp $ * $Id: rf230bb.h,v 1.4 2010/12/03 20:42:01 dak664 Exp $
*/ */
#ifndef RADIO_H #ifndef RADIO_H
@ -211,8 +211,6 @@ uint8_t rf230_get_raw_rssi(void);
#define rf230_rssi rf230_get_raw_rssi #define rf230_rssi rf230_get_raw_rssi
#define delay_us( us ) ( _delay_loop_2( ( F_CPU / 4000000UL ) * ( us ) ) )
#endif #endif
/** @} */ /** @} */
/*EOF*/ /*EOF*/

4
platform/avr-raven/contiki-conf.h
View file

@ -102,6 +102,7 @@
#define NETSTACK_CONF_RDC sicslowmac_driver #define NETSTACK_CONF_RDC sicslowmac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define CHANNEL_802_15_4 26
#define RF230_CONF_AUTOACK 1 #define RF230_CONF_AUTOACK 1
#define RF230_CONF_AUTORETRIES 2 #define RF230_CONF_AUTORETRIES 2
#define SICSLOWPAN_CONF_FRAG 1 #define SICSLOWPAN_CONF_FRAG 1
@ -116,6 +117,7 @@
#define NETSTACK_CONF_RDC contikimac_driver #define NETSTACK_CONF_RDC contikimac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define CHANNEL_802_15_4 26
#define RF230_CONF_AUTOACK 0 #define RF230_CONF_AUTOACK 0
#define RF230_CONF_AUTORETRIES 0 #define RF230_CONF_AUTORETRIES 0
@ -125,6 +127,7 @@
#define NETSTACK_CONF_RDC cxmac_driver #define NETSTACK_CONF_RDC cxmac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define CHANNEL_802_15_4 26
#define RF230_CONF_AUTOACK 0 #define RF230_CONF_AUTOACK 0
#define RF230_CONF_AUTORETRIES 0 #define RF230_CONF_AUTORETRIES 0
#define MAC_CONF_CHANNEL_CHECK_RATE 8 #define MAC_CONF_CHANNEL_CHECK_RATE 8
@ -189,7 +192,6 @@
//#define RF230_MIN_RX_POWER 30 //#define RF230_MIN_RX_POWER 30
#define UIP_CONF_ROUTER 1 #define UIP_CONF_ROUTER 1
#define UIP_CONF_IPV6_RPL 1
/* Handle 10 neighbors */ /* Handle 10 neighbors */
#define UIP_CONF_DS6_NBR_NBU 10 #define UIP_CONF_DS6_NBR_NBU 10

5
platform/avr-raven/contiki-raven-main.c
View file

@ -126,7 +126,12 @@ static uint8_t get_channel_from_eeprom() {
if(eeprom_channel==~eeprom_check) if(eeprom_channel==~eeprom_check)
return eeprom_channel; return eeprom_channel;
#ifdef CHANNEL_802_15_4
return(CHANNEL_802_15_4);
#else
return 26; return 26;
#endif
} }
static bool get_mac_from_eeprom(uint8_t* macptr) { static bool get_mac_from_eeprom(uint8_t* macptr) {

12
platform/avr-ravenusb/cdc_task.c
View file

@ -298,11 +298,9 @@ void menu_process(char c)
if(settings_set_uint8(SETTINGS_KEY_CHANNEL, tempchannel)!=SETTINGS_STATUS_OK) { if(settings_set_uint8(SETTINGS_KEY_CHANNEL, tempchannel)!=SETTINGS_STATUS_OK) {
PRINTF_P(PSTR("\n\rChannel changed to %d, but unable to store in EEPROM!\n\r"),tempchannel); PRINTF_P(PSTR("\n\rChannel changed to %d, but unable to store in EEPROM!\n\r"),tempchannel);
} else } else
#else #else
AVR_ENTER_CRITICAL_REGION();
eeprom_write_byte((uint8_t *) 9, tempchannel); //Write channel eeprom_write_byte((uint8_t *) 9, tempchannel); //Write channel
eeprom_write_byte((uint8_t *)10, ~tempchannel); //Bit inverse as check eeprom_write_byte((uint8_t *)10, ~tempchannel); //Bit inverse as check
AVR_LEAVE_CRITICAL_REGION();
#endif #endif
PRINTF_P(PSTR("\n\rChannel changed to %d and stored in EEPROM.\n\r"),tempchannel); PRINTF_P(PSTR("\n\rChannel changed to %d and stored in EEPROM.\n\r"),tempchannel);
} }
@ -446,8 +444,16 @@ void menu_process(char c)
#include "rpl.h" #include "rpl.h"
extern uip_ds6_nbr_t uip_ds6_nbr_cache[]; extern uip_ds6_nbr_t uip_ds6_nbr_cache[];
extern uip_ds6_route_t uip_ds6_routing_table[]; extern uip_ds6_route_t uip_ds6_routing_table[];
extern uip_ds6_netif_t uip_ds6_if;
case 'N': case 'N':
{ uint8_t i,j; { uint8_t i,j;
PRINTF_P(PSTR("\n\rAddresses [%u max]\n\r"),UIP_DS6_ADDR_NB);
for (i=0;i<UIP_DS6_ADDR_NB;i++) {
if (uip_ds6_if.addr_list[i].isused) {
ipaddr_add(&uip_ds6_if.addr_list[i].ipaddr);
PRINTF_P(PSTR("\n\r"));
}
}
PRINTF_P(PSTR("\n\rNeighbors [%u max]\n\r"),UIP_DS6_NBR_NB); PRINTF_P(PSTR("\n\rNeighbors [%u max]\n\r"),UIP_DS6_NBR_NB);
for(i = 0,j=1; i < UIP_DS6_NBR_NB; i++) { for(i = 0,j=1; i < UIP_DS6_NBR_NB; i++) {
if(uip_ds6_nbr_cache[i].isused) { if(uip_ds6_nbr_cache[i].isused) {

7
platform/avr-ravenusb/contiki-conf.h
View file

@ -241,6 +241,7 @@ extern void mac_log_802_15_4_rx(const uint8_t* buffer, size_t total_len);
#define NETSTACK_CONF_RDC sicslowmac_driver #define NETSTACK_CONF_RDC sicslowmac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define CHANNEL_802_15_4 26
#define RF230_CONF_AUTOACK 1 #define RF230_CONF_AUTOACK 1
#define RF230_CONF_AUTORETRIES 2 #define RF230_CONF_AUTORETRIES 2
#define QUEUEBUF_CONF_NUM 1 #define QUEUEBUF_CONF_NUM 1
@ -254,6 +255,7 @@ extern void mac_log_802_15_4_rx(const uint8_t* buffer, size_t total_len);
#define NETSTACK_CONF_RDC contikimac_driver #define NETSTACK_CONF_RDC contikimac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define 802_15_4_CHANNEL 26
#define RF230_CONF_AUTOACK 0 #define RF230_CONF_AUTOACK 0
#define RF230_CONF_AUTORETRIES 0 #define RF230_CONF_AUTORETRIES 0
@ -263,6 +265,7 @@ extern void mac_log_802_15_4_rx(const uint8_t* buffer, size_t total_len);
#define NETSTACK_CONF_RDC cxmac_driver #define NETSTACK_CONF_RDC cxmac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define 802_15_4_CHANNEL 26
#define RF230_CONF_AUTOACK 0 #define RF230_CONF_AUTOACK 0
#define RF230_CONF_AUTORETRIES 0 #define RF230_CONF_AUTORETRIES 0
#define MAC_CONF_CHANNEL_CHECK_RATE 8 #define MAC_CONF_CHANNEL_CHECK_RATE 8
@ -282,7 +285,7 @@ extern void mac_log_802_15_4_rx(const uint8_t* buffer, size_t total_len);
//#pragma mark RPL Settings //#pragma mark RPL Settings
/* ************************************************************************** */ /* ************************************************************************** */
#if UIP_CONF_IPV6 //Allows hello-world ip4 to compile #if UIP_CONF_IPV6 //Allows hello-world ip4 to compile
#define UIP_CONF_IPV6_RPL 0 #define UIP_CONF_IPV6_RPL 0
#endif #endif
#if UIP_CONF_IPV6_RPL #if UIP_CONF_IPV6_RPL
@ -312,7 +315,7 @@ extern void mac_log_802_15_4_rx(const uint8_t* buffer, size_t total_len);
//#define RF230_MIN_RX_POWER 30 //#define RF230_MIN_RX_POWER 30
#define UIP_CONF_ROUTER 1 #define UIP_CONF_ROUTER 1
#define UIP_CONF_ROUTER_RECEIVE_RA 1 #define UIP_CONF_ROUTER_RECEIVE_RA 0
#define RPL_BORDER_ROUTER 1 #define RPL_BORDER_ROUTER 1
#define RPL_CONF_STATS 0 #define RPL_CONF_STATS 0
#define UIP_CONF_BUFFER_SIZE 1300 #define UIP_CONF_BUFFER_SIZE 1300

32
platform/avr-ravenusb/contiki-raven-main.c
View file

@ -147,37 +147,41 @@ uint16_t dag_id[] PROGMEM = {0x1111, 0x1100, 0, 0, 0, 0, 0, 0x0011};
PROCESS(border_router_process, "RPL Border Router"); PROCESS(border_router_process, "RPL Border Router");
PROCESS_THREAD(border_router_process, ev, data) PROCESS_THREAD(border_router_process, ev, data)
{ {
rpl_dag_t *dag;
PROCESS_BEGIN(); PROCESS_BEGIN();
PROCESS_PAUSE(); PROCESS_PAUSE();
// printf_P(PSTR("%d neighbors"), UIP_DS6_ADDR_NB); { rpl_dag_t *dag;
{ char buf[sizeof(dag_id)]; char buf[sizeof(dag_id)];
memcpy_P(buf,dag_id,sizeof(dag_id)); memcpy_P(buf,dag_id,sizeof(dag_id));
dag = rpl_set_root((uip_ip6addr_t *)buf); dag = rpl_set_root((uip_ip6addr_t *)buf);
}
#if UIP_CONF_IPV6_RPL
/* Assign bbbb::11 to the uip stack, and bbbb::1 to the host network interface, e.g. $ip -6 address add bbbb::1/64 dev usb0 */ /* Assign bbbb::11 to the uip stack, and bbbb::1 to the host network interface, e.g. $ip -6 address add bbbb::1/64 dev usb0 */
/* $ifconfig usb0 -arp on Ubuntu to skip the neighbor solicitations. Don't know how to skip NS on Windows yet. */ /* $ifconfig usb0 -arp on Ubuntu to skip the neighbor solicitations. Add explicit neighbors on other OSs */
if(dag != NULL) { if(dag != NULL) {
PRINTF("created a new RPL dag\n");
#if UIP_CONF_ROUTER_RECEIVE_RA
//Contiki stack will shut down until assigned an address from the interface RA
//Currently this requires changes in the core rpl-icmp6.c to pass the link-local RA broadcast
#else
uip_ip6addr_t ipaddr; uip_ip6addr_t ipaddr;
uip_ip6addr(&ipaddr, 0xbbbb, 0, 0, 0, 0, 0, 0, 0x11); uip_ip6addr(&ipaddr, 0xbbbb, 0, 0, 0, 0, 0, 0, 0x11);
// uip_ds6_addr_add(&ipaddr, 0, ADDR_AUTOCONF);
uip_ds6_addr_add(&ipaddr, 0, ADDR_MANUAL); uip_ds6_addr_add(&ipaddr, 0, ADDR_MANUAL);
rpl_set_prefix(dag, &ipaddr, 64); rpl_set_prefix(dag, &ipaddr, 64);
PRINTF("created a new RPL dag\n");
}
#endif #endif
}
}
/* The border router runs with a 100% duty cycle in order to ensure high /* The border router runs with a 100% duty cycle in order to ensure high
packet reception rates. */ packet reception rates. */
// NETSTACK_MAC.off(1); // NETSTACK_MAC.off(1);
while(1) { while(1) {
PROCESS_YIELD(); PROCESS_YIELD();
// rpl_repair_dag(rpl_get_dag(RPL_ANY_INSTANCE)); // rpl_set_prefix(rpl_get_dag(RPL_ANY_INSTANCE), &ipaddr, 64);
// rpl_repair_dag(rpl_get_dag(RPL_ANY_INSTANCE));
} }
@ -219,7 +223,13 @@ static uint8_t get_channel_from_eeprom() {
if(eeprom_channel==~eeprom_check) if(eeprom_channel==~eeprom_check)
return eeprom_channel; return eeprom_channel;
#ifdef CHANNEL_802_15_4
return(CHANNEL_802_15_4);
#else
return 26; return 26;
#endif
#endif #endif
} }

8
platform/avr-ravenusb/httpd-simple-avr.c
View file

@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* $Id: httpd-simple-avr.c,v 1.6 2010/12/01 16:23:55 dak664 Exp $ * $Id: httpd-simple-avr.c,v 1.7 2010/12/03 20:42:02 dak664 Exp $
*/ */
/** /**
@ -253,7 +253,7 @@ extern uip_ds6_route_t uip_ds6_routing_table[];
static static
PT_THREAD(generate_routes(struct httpd_state *s)) PT_THREAD(generate_routes(struct httpd_state *s))
{ {
int i; uint8_t i=0;
PSOCK_BEGIN(&s->sout); PSOCK_BEGIN(&s->sout);
PSOCK_GENERATOR_SEND(&s->sout, generate_string_P, TOP1); PSOCK_GENERATOR_SEND(&s->sout, generate_string_P, TOP1);
@ -262,6 +262,8 @@ PT_THREAD(generate_routes(struct httpd_state *s))
#if UIP_CONF_IPV6 //allow ip4 builds #if UIP_CONF_IPV6 //allow ip4 builds
blen = 0; blen = 0;
ADD("<h2>Neighbors [%u max]</h2>",UIP_DS6_NBR_NB); ADD("<h2>Neighbors [%u max]</h2>",UIP_DS6_NBR_NB);
PSOCK_GENERATOR_SEND(&s->sout, generate_string, buf);
blen = 0;
for(i = 0; i < UIP_DS6_NBR_NB; i++) { for(i = 0; i < UIP_DS6_NBR_NB; i++) {
if(uip_ds6_nbr_cache[i].isused) { if(uip_ds6_nbr_cache[i].isused) {
ipaddr_add(&uip_ds6_nbr_cache[i].ipaddr); ipaddr_add(&uip_ds6_nbr_cache[i].ipaddr);
@ -284,6 +286,8 @@ PT_THREAD(generate_routes(struct httpd_state *s))
blen=0; blen=0;
ipaddr_add(&uip_ds6_routing_table[i].nexthop); ipaddr_add(&uip_ds6_routing_table[i].nexthop);
if(uip_ds6_routing_table[i].state.lifetime < 600) { if(uip_ds6_routing_table[i].state.lifetime < 600) {
PSOCK_GENERATOR_SEND(&s->sout, generate_string, buf);
blen=0;
ADD(") %lus<br>", uip_ds6_routing_table[i].state.lifetime); ADD(") %lus<br>", uip_ds6_routing_table[i].state.lifetime);
} else { } else {
ADD(")<br>"); ADD(")<br>");

8
platform/avr-zigbit/contiki-avr-zigbit-main.c
View file

@ -122,15 +122,17 @@ init_lowlevel(void)
rimeaddr_t addr; rimeaddr_t addr;
memset(&addr, 0, sizeof(rimeaddr_t)); memset(&addr, 0, sizeof(rimeaddr_t));
AVR_ENTER_CRITICAL_REGION();
eeprom_read_block ((void *)&addr.u8, &mac_address, 8); eeprom_read_block ((void *)&addr.u8, &mac_address, 8);
AVR_LEAVE_CRITICAL_REGION();
#if UIP_CONF_IPV6 #if UIP_CONF_IPV6
memcpy(&uip_lladdr.addr, &addr.u8, 8); memcpy(&uip_lladdr.addr, &addr.u8, 8);
#endif #endif
rf230_set_pan_addr(IEEE802154_PANID, 0, (uint8_t *)&addr.u8); rf230_set_pan_addr(IEEE802154_PANID, 0, (uint8_t *)&addr.u8);
rf230_set_channel(24); #ifdef CHANNEL_802_15_4
rf230_set_channel(CHANNEL_802_15_4);
#else
rf230_set_channel(26);
#endif
rimeaddr_set_node_addr(&addr); rimeaddr_set_node_addr(&addr);

2
platform/avr-zigbit/contiki-conf.h
View file

@ -43,7 +43,6 @@
#define __CONTIKI_CONF_H__ #define __CONTIKI_CONF_H__
/* MCU and clock rate */ /* MCU and clock rate */
#define MCU_MHZ 8
#define PLATFORM PLATFORM_AVR #define PLATFORM PLATFORM_AVR
#define HARWARE_REVISION ZIGBIT #define HARWARE_REVISION ZIGBIT
@ -97,6 +96,7 @@
#define NETSTACK_CONF_RDC sicslowmac_driver #define NETSTACK_CONF_RDC sicslowmac_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define NETSTACK_CONF_RADIO rf230_driver #define NETSTACK_CONF_RADIO rf230_driver
#define CHANNEL_802_15_4 26
#define RF230_CONF_AUTOACK 1 #define RF230_CONF_AUTOACK 1
#define RF230_CONF_AUTORETRIES 2 #define RF230_CONF_AUTORETRIES 2
#define SICSLOWPAN_CONF_FRAG 1 #define SICSLOWPAN_CONF_FRAG 1