diff --git a/cpu/x86/Makefile.x86_quarkX1000 b/cpu/x86/Makefile.x86_quarkX1000 index e5c0b1801..7205a446a 100644 --- a/cpu/x86/Makefile.x86_quarkX1000 +++ b/cpu/x86/Makefile.x86_quarkX1000 @@ -3,7 +3,7 @@ include $(CONTIKI)/cpu/x86/Makefile.x86_common CONTIKI_CPU_DIRS += drivers/legacy_pc drivers/quarkX1000 init/legacy_pc CONTIKI_SOURCEFILES += bootstrap_quarkX1000.S rtc.c pit.c pic.c irq.c nmi.c pci.c uart-16x50.c uart.c gpio.c i2c.c eth.c shared-isr.c -CONTIKI_SOURCEFILES += msg-bus.c +CONTIKI_SOURCEFILES += imr.c msg-bus.c CFLAGS += -m32 -march=i586 -mtune=i586 LDFLAGS += -m32 -Xlinker -T -Xlinker $(CONTIKI)/cpu/x86/quarkX1000.ld diff --git a/cpu/x86/drivers/quarkX1000/imr.c b/cpu/x86/drivers/quarkX1000/imr.c new file mode 100644 index 000000000..03c43a0c0 --- /dev/null +++ b/cpu/x86/drivers/quarkX1000/imr.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2015-2016, Intel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "imr.h" +#include "msg-bus.h" + +#define MEM_MANAGER_PORT 5 + +#define IMR_BASE_OFFSET 0x40 +#define IMR_REG_COUNT 4 + +#define IMR_LO_OFFSET 0 +#define IMR_HI_OFFSET 1 +#define IMR_RDMSK_OFFSET 2 +#define IMR_WRMSK_OFFSET 3 + +/*---------------------------------------------------------------------------*/ +/** + * \brief Read the contents of the specified IMR. + */ +quarkX1000_imr_t +quarkX1000_imr_read(uint32_t imr_idx) +{ + quarkX1000_imr_t imr; + uint32_t reg_base = IMR_BASE_OFFSET + (IMR_REG_COUNT * imr_idx); + + assert(imr_idx < QUARKX1000_IMR_CNT); + + quarkX1000_msg_bus_read(MEM_MANAGER_PORT, + reg_base + IMR_LO_OFFSET, &imr.lo.raw); + quarkX1000_msg_bus_read(MEM_MANAGER_PORT, + reg_base + IMR_HI_OFFSET, &imr.hi.raw); + quarkX1000_msg_bus_read(MEM_MANAGER_PORT, + reg_base + IMR_RDMSK_OFFSET, &imr.rdmsk.raw); + quarkX1000_msg_bus_read(MEM_MANAGER_PORT, + reg_base + IMR_WRMSK_OFFSET, &imr.wrmsk.raw); + + return imr; +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Overwrite the contents of the specified IMR. + */ +void +quarkX1000_imr_write(uint32_t imr_idx, quarkX1000_imr_t imr) +{ + uint32_t reg_base = IMR_BASE_OFFSET + (IMR_REG_COUNT * imr_idx); + + assert(imr_idx < QUARKX1000_IMR_CNT); + + quarkX1000_msg_bus_write(MEM_MANAGER_PORT, + reg_base + IMR_HI_OFFSET, imr.hi.raw); + quarkX1000_msg_bus_write(MEM_MANAGER_PORT, + reg_base + IMR_RDMSK_OFFSET, imr.rdmsk.raw); + quarkX1000_msg_bus_write(MEM_MANAGER_PORT, + reg_base + IMR_WRMSK_OFFSET, imr.wrmsk.raw); + /* This register must be programmed last, in case it sets the lock bit. */ + quarkX1000_msg_bus_write(MEM_MANAGER_PORT, + reg_base + IMR_LO_OFFSET, imr.lo.raw); +} +/*---------------------------------------------------------------------------*/ diff --git a/cpu/x86/drivers/quarkX1000/imr.h b/cpu/x86/drivers/quarkX1000/imr.h new file mode 100644 index 000000000..f5ddef3e2 --- /dev/null +++ b/cpu/x86/drivers/quarkX1000/imr.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2015-2016, Intel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CPU_X86_DRIVERS_QUARKX1000_IMR_H_ +#define CPU_X86_DRIVERS_QUARKX1000_IMR_H_ + +#include + +typedef union quarkX1000_imr_lo { + struct { + uint32_t : 2; + uint32_t addr : 22; + uint32_t : 7; + uint32_t lock : 1; + }; + uint32_t raw; +} quarkX1000_imr_lo_t; + +typedef union quarkX1000_imr_hi { + struct { + uint32_t : 2; + uint32_t addr : 22; + uint32_t : 8; + }; + uint32_t raw; +} quarkX1000_imr_hi_t; + +/* Amount to shift imr_lo/hi.addr left to obtain the bound address */ +#define QUARKX1000_IMR_SHAMT 10 + +typedef union quarkX1000_imr_rdmsk { + struct { + uint32_t cpu0 : 1; + uint32_t cpu_0 : 1; + uint32_t : 6; + uint32_t vc0_sai_id0 : 1; + uint32_t vc0_sai_id1 : 1; + uint32_t vc0_sai_id2 : 1; + uint32_t vc0_sai_id3 : 1; + uint32_t vc1_sai_id0 : 1; + uint32_t vc1_sai_id1 : 1; + uint32_t vc1_sai_id2 : 1; + uint32_t vc1_sai_id3 : 1; + uint32_t : 13; + uint32_t punit : 1; + uint32_t : 1; + uint32_t esram_flush_init : 1; + }; + uint32_t raw; +} quarkX1000_imr_rdmsk_t; + +typedef union quarkX1000_imr_wrmsk { + struct { + uint32_t cpu0 : 1; + uint32_t cpu_0 : 1; + uint32_t : 6; + uint32_t vc0_sai_id0 : 1; + uint32_t vc0_sai_id1 : 1; + uint32_t vc0_sai_id2 : 1; + uint32_t vc0_sai_id3 : 1; + uint32_t vc1_sai_id0 : 1; + uint32_t vc1_sai_id1 : 1; + uint32_t vc1_sai_id2 : 1; + uint32_t vc1_sai_id3 : 1; + uint32_t : 13; + uint32_t punit : 1; + uint32_t cpu_snoop : 1; + uint32_t esram_flush_init : 1; + }; + uint32_t raw; +} quarkX1000_imr_wrmsk_t; + +/* Refer to Intel Quark SoC X1000 Datasheet, Section 12.7.4 for more details on + * the IMR registers. + */ +typedef struct quarkX1000_imr { + quarkX1000_imr_lo_t lo; + quarkX1000_imr_hi_t hi; + quarkX1000_imr_rdmsk_t rdmsk; + quarkX1000_imr_wrmsk_t wrmsk; +} quarkX1000_imr_t; + +/* The Intel Quark SoC X1000 defines eight general IMRs. */ +#define QUARKX1000_IMR_CNT 8 + +/* Routines for accessing the Isolated Memory Region (IMR) feature. + * + * The Intel Quark X1000 SoC includes support for Isolated Memory Regions + * (IMRs), which are specified using range registers and associated + * control registers that are accessible via the message bus. + * + * Refer to Intel Quark SoC X1000 Datasheet, Section 12.2 for more information. + */ + +quarkX1000_imr_t quarkX1000_imr_read(uint32_t imr_idx); +void quarkX1000_imr_write(uint32_t imr_idx, quarkX1000_imr_t imr); + +#endif /* CPU_X86_DRIVERS_QUARKX1000_IMR_H_ */ diff --git a/platform/galileo/README.md b/platform/galileo/README.md index 63c929c4f..95d2f6353 100644 --- a/platform/galileo/README.md +++ b/platform/galileo/README.md @@ -34,6 +34,7 @@ Device drivers: * GPIO (default pinmux configuration is listed in platform/galileo/drivers/galileo-pinmux.c) * Intel Quark X1000 SoC message bus + * Isolated Memory Regions (IMRs) Contiki APIs: * Clock module