Merge pull request #416 from oliverschmidt/master
Added missing fixup & removed wait loop from poll.
This commit is contained in:
commit
497e7fbbac
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@ -79,6 +79,7 @@ fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25, fixup27-fixup26
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fixups = * - fixup
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@ -169,26 +170,33 @@ fixup08:sta data
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;---------------------------------------------------------------------
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poll:
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; Check for completion of previous command
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; Socket 0 Command Register: = 0 ?
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jsr set_addrcmdreg0
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fixup09:lda data
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beq :++
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; No data available
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lda #$00
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: tax
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rts
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; Socket RX Received Size Register: != 0 ?
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: ldy #$26 ; Socket RX Received Size Register
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jsr set_addrsocket0
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fixup10:lda data ; Hibyte
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fixup11:ora data ; Lobyte
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beq :--
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; Process the incoming data
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; -------------------------
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; Set parameters for receiving data
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lda #>$6000 ; Socket 0 RX Base Address
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ldx #$00 ; Read
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jsr set_parameters
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; Socket RX Received Size Register: != 0 ?
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ldy #$26 ; Socket RX Received Size Register
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jsr set_addrsocket0
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fixup09:lda data ; Hibyte
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fixup10:ora data ; Lobyte
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bne :+
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; No data available
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tax
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rts
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; Process the incoming data
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; -------------------------
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: ; ldy #$28 ; Socket RX Read Pointer Register
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; ldy #$28 ; Socket RX Read Pointer Register
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; jsr set_addrsocket0
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; Calculate and set pyhsical address
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@ -239,13 +247,13 @@ common: jsr set_addrsocket0
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tax
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lda reg+1
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adc adv+1
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fixup11:sta data ; Hibyte
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fixup12:stx data ; Lobyte
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fixup12:sta data ; Hibyte
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fixup13:stx data ; Lobyte
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; Set command register
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tya ; Restore command
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jsr set_addrcmdreg0
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fixup13:sta data
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fixup14:sta data
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; Return data length (will be ignored for send)
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lda len
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@ -268,11 +276,17 @@ send:
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ldx #$01 ; Write
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jsr set_parameters
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; Wait for completion of previous command
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; Socket 0 Command Register: = 0 ?
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: jsr set_addrcmdreg0
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fixup15:lda data
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bne :-
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; Socket 0 TX Free Size Register: < length ?
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: ldy #$20
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jsr set_addrsocket0
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fixup14:lda data ; Hibyte
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fixup15:ldx data ; Lobyte
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fixup16:lda data ; Hibyte
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fixup17:ldx data ; Lobyte
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cpx len
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sbc len+1
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bcc :-
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@ -302,16 +316,16 @@ exit:
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;---------------------------------------------------------------------
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set_addrphysical:
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fixup16:lda data ; Hibyte
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fixup17:ldy data ; Lobyte
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fixup18:lda data ; Hibyte
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fixup19:ldy data ; Lobyte
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sta reg+1
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sty reg
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and #>$1FFF ; Socket Mask Address (hibyte)
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ora bas ; Socket Base Address (hibyte)
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tax
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set_addr:
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fixup18:stx addr ; Hibyte
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fixup19:sty addr+1 ; Lobyte
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fixup20:stx addr ; Hibyte
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fixup21:sty addr+1 ; Lobyte
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rts
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set_addrcmdreg0:
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@ -326,8 +340,8 @@ set_addrbase:
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beq set_addr ; Always
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get_datacheckaddr:
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fixup20:lda data
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ldx addr ; Hibyte
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fixup22:lda data
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fixup23:ldx addr ; Hibyte
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cpx lim ; Socket memory limit (hibyte)
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bcs set_addrbase
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rts
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@ -347,12 +361,6 @@ set_parameters:
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ldx bufaddr+1
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sta ptr
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stx ptr+1
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; Wait for previous command to complete
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; Socket 0 Command Register: = 0 ?
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: jsr set_addrcmdreg0
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fixup21:lda data
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bne :-
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rts
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;---------------------------------------------------------------------
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@ -372,10 +380,10 @@ mov_data:
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; R/W without address wraparound possible because
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; highest R/W address > actual R/W address ?
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; sec
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fixup22:sbc addr+1 ; Lobyte
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fixup24:sbc addr+1 ; Lobyte
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tay
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txa
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fixup23:sbc addr ; Hibyte
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fixup25:sbc addr ; Hibyte
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tax
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tya
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bcs :+
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@ -436,7 +444,7 @@ rw_data:eor #$FF ; Two's complement part 1
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; Read data
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:
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fixup24:lda data
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fixup26:lda data
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sta (ptr),y
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iny
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bne :-
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@ -447,7 +455,7 @@ fixup24:lda data
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; Write data
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: lda (ptr),y
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fixup25:sta data
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fixup27:sta data
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iny
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bne :-
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inc ptr+1
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