commit
48e987baac
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@ -52,6 +52,7 @@ CONTIKI_CPU_SOURCEFILES += nvic.c cpu.c sys-ctrl.c gpio.c ioc.c spi.c adc.c
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CONTIKI_CPU_SOURCEFILES += cc2538-rf.c udma.c lpm.c
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CONTIKI_CPU_SOURCEFILES += dbg.c ieee-addr.c
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CONTIKI_CPU_SOURCEFILES += slip-arch.c slip.c
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CONTIKI_CPU_SOURCEFILES += i2c.c
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DEBUG_IO_SOURCEFILES += dbg-printf.c dbg-snprintf.c dbg-sprintf.c strformat.c
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254
cpu/cc2538/dev/i2c.c
Normal file
254
cpu/cc2538/dev/i2c.c
Normal file
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@ -0,0 +1,254 @@
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/*
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* Copyright (c) 2015, Mehdi Migault
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
*
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||||
* 3. Neither the name of the copyright holder nor the names of its
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||||
* contributors may be used to endorse or promote products derived
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||||
* from this software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-i2c cc2538 I2C Control
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* @{
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*
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* \file
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* Implementation file of the I2C Control module
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*
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* \author
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* Mehdi Migault
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*/
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#include "i2c.h"
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#include <stdint.h>
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#include "clock.h"
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/*---------------------------------------------------------------------------*/
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/* Additional functions */
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static uint32_t
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get_sys_clock(void)
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{
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/* Get the clock status diviser */
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return SYS_CTRL_32MHZ /
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((REG(SYS_CTRL_CLOCK_STA) & SYS_CTRL_CLOCK_STA_SYS_DIV) + 1);
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_init(uint8_t port_sda, uint8_t pin_sda, uint8_t port_scl, uint8_t pin_scl,
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uint32_t bus_speed)
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{
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/* Enable I2C clock in different modes */
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REG(SYS_CTRL_RCGCI2C) |= 1; /* Run mode */
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/* Reset I2C peripheral */
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REG(SYS_CTRL_SRI2C) |= 1; /* Reset position */
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/* Delay for a little bit */
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clock_delay_usec(50);
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REG(SYS_CTRL_SRI2C) &= ~1; /* Normal position */
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/* Set pins in input */
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GPIO_SET_INPUT(GPIO_PORT_TO_BASE(port_sda), GPIO_PIN_MASK(pin_sda));
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GPIO_SET_INPUT(GPIO_PORT_TO_BASE(port_scl), GPIO_PIN_MASK(pin_scl));
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/* Set peripheral control for the pins */
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(port_sda), GPIO_PIN_MASK(pin_sda));
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(port_scl), GPIO_PIN_MASK(pin_scl));
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/* Set the pad to no drive type */
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ioc_set_over(port_sda, pin_sda, IOC_OVERRIDE_DIS);
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ioc_set_over(port_scl, pin_scl, IOC_OVERRIDE_DIS);
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/* Set pins as peripheral inputs */
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REG(IOC_I2CMSSDA) = ioc_input_sel(port_sda, pin_sda);
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REG(IOC_I2CMSSCL) = ioc_input_sel(port_scl, pin_scl);
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/* Set pins as peripheral outputs */
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ioc_set_sel(port_sda, pin_sda, IOC_PXX_SEL_I2C_CMSSDA);
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ioc_set_sel(port_scl, pin_scl, IOC_PXX_SEL_I2C_CMSSCL);
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/* Enable the I2C master module */
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i2c_master_enable();
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/* t the master clock frequency */
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i2c_set_frequency(bus_speed);
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_master_enable(void)
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{
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REG(I2CM_CR) |= 0x10; /* Set MFE bit */
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_master_disable(void)
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{
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REG(I2CM_CR) &= ~0x10; /* Reset MFE bit */
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_set_frequency(uint32_t freq)
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{
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/* Peripheral clock setting, using the system clock */
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REG(I2CM_TPR) = ((get_sys_clock() + (2 * 10 * freq) - 1) /
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(2 * 10 * freq)) - 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_master_set_slave_address(uint8_t slave_addr, uint8_t access_mode)
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{
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if(access_mode) {
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REG(I2CM_SA) = ((slave_addr << 1) | 1);
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} else {
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REG(I2CM_SA) = (slave_addr << 1);
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}
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_master_data_put(uint8_t data)
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{
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REG(I2CM_DR) = data;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_master_data_get(void)
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{
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return REG(I2CM_DR);
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}
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/*---------------------------------------------------------------------------*/
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void
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i2c_master_command(uint8_t cmd)
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{
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REG(I2CM_CTRL) = cmd;
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/* Here we need a delay, otherwise the I2C module keep the receiver mode */
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clock_delay_usec(1);
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_master_busy(void)
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{
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return REG(I2CM_STAT) & I2CM_STAT_BUSY;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_master_error(void)
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{
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uint8_t temp = REG(I2CM_STAT); /* Get all status */
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if(temp & I2CM_STAT_BUSY) { /* No valid if BUSY bit is set */
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return I2C_MASTER_ERR_NONE;
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} else if(temp & (I2CM_STAT_ERROR | I2CM_STAT_ARBLST)) {
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return temp; /* Compare later */
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}
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return I2C_MASTER_ERR_NONE;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_single_send(uint8_t slave_addr, uint8_t data)
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{
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i2c_master_set_slave_address(slave_addr, I2C_SEND);
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i2c_master_data_put(data);
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i2c_master_command(I2C_MASTER_CMD_SINGLE_SEND);
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while(i2c_master_busy());
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/* Return the STAT register of I2C module if error occured, I2C_MASTER_ERR_NONE otherwise */
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return i2c_master_error();
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_single_receive(uint8_t slave_addr, uint8_t *data)
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{
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uint32_t temp;
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i2c_master_set_slave_address(slave_addr, I2C_RECEIVE);
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i2c_master_command(I2C_MASTER_CMD_SINGLE_RECEIVE);
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while(i2c_master_busy());
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temp = i2c_master_error();
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if(temp == I2C_MASTER_ERR_NONE) {
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*data = i2c_master_data_get();
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}
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return temp;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_burst_send(uint8_t slave_addr, uint8_t *data, uint8_t len)
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{
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uint8_t sent;
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if((len == 0) || (data == NULL)) {
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return I2CM_STAT_INVALID;
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}
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if(len == 1) {
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return i2c_single_send(slave_addr, data[0]);
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}
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i2c_master_set_slave_address(slave_addr, I2C_SEND);
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i2c_master_data_put(data[0]);
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i2c_master_command(I2C_MASTER_CMD_BURST_SEND_START);
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while(i2c_master_busy());
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if(i2c_master_error() == I2C_MASTER_ERR_NONE) {
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for(sent = 1; sent <= (len - 2); sent++) {
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i2c_master_data_put(data[sent]);
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i2c_master_command(I2C_MASTER_CMD_BURST_SEND_CONT);
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while(i2c_master_busy());
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}
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/* This should be the last byte, stop sending */
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i2c_master_data_put(data[len - 1]);
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i2c_master_command(I2C_MASTER_CMD_BURST_SEND_FINISH);
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while(i2c_master_busy());
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}
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/* Return the STAT register of I2C module if error occurred, I2C_MASTER_ERR_NONE otherwise */
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return i2c_master_error();
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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i2c_burst_receive(uint8_t slave_addr, uint8_t *data, uint8_t len)
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{
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uint8_t recv = 0;
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if((len == 0) || data == NULL) {
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return I2CM_STAT_INVALID;
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}
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if(len == 1) {
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return i2c_single_receive(slave_addr, &data[0]);
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}
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i2c_master_set_slave_address(slave_addr, I2C_RECEIVE);
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i2c_master_command(I2C_MASTER_CMD_BURST_RECEIVE_START);
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while(i2c_master_busy());
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if(i2c_master_error() == I2C_MASTER_ERR_NONE) {
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data[0] = i2c_master_data_get();
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/* If we got 2 or more bytes pending to be received, keep going*/
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for(recv = 1; recv <= (len - 2); recv++) {
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i2c_master_command(I2C_MASTER_CMD_BURST_RECEIVE_CONT);
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while(i2c_master_busy());
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data[recv] = i2c_master_data_get();
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}
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/* This should be the last byte, stop receiving */
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i2c_master_command(I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
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while(i2c_master_busy());
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data[len - 1] = i2c_master_data_get();
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}
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return i2c_master_error();
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}
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/*---------------------------------------------------------------------------*/
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/** @} */
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240
cpu/cc2538/dev/i2c.h
Normal file
240
cpu/cc2538/dev/i2c.h
Normal file
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@ -0,0 +1,240 @@
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/*
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* Copyright (c) 2015, Mehdi Migault
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* All rights reserved.
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||||
*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
||||
* OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-i2c cc2538 I2C Control
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*
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* cc2538 I2C Control Module
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* @{
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*
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* \file
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* Header file with declarations for the I2C Control module
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*
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* \author
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* Mehdi Migault
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*/
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#ifndef I2C_H_
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#define I2C_H_
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#include "reg.h"
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#include "sys-ctrl.h"
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#include "gpio.h"
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#include "ioc.h"
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#include <stdio.h> /* For debug */
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#include "clock.h" /* For temporisation */
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/*---------------------------------------------------------------------------*/
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/** \name I2C Master commands
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* @{
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*/
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#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007
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#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007
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#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003
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#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001
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#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005
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#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004
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#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b
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#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009
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#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005
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#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000004
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name I2C Master status flags
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* @{
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*/
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#define I2C_MASTER_ERR_NONE 0
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#define I2CM_STAT_BUSY 0x00000001
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#define I2CM_STAT_ERROR 0x00000002
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#define I2CM_STAT_ADRACK 0x00000004
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#define I2CM_STAT_DATACK 0x00000008
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#define I2CM_STAT_ARBLST 0x00000010
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#define I2CM_STAT_IDLE 0x00000020
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#define I2CM_STAT_BUSBSY 0x00000040
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#define I2CM_STAT_INVALID 0x00000080
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name I2C registers
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* @{
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*/
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#define I2CM_CR 0x40020020 /* I2C master config */
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#define I2CM_TPR 0x4002000C /* I2C master timer period */
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#define I2CM_SA 0x40020000 /* I2C master slave address */
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#define I2CM_DR 0x40020008 /* I2C master data */
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#define I2CM_CTRL 0x40020004 /* Master control in write */
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#define I2CM_STAT I2CM_CTRL /* Master status in read */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name I2C Miscellaneous
|
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* @{
|
||||
*/
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#define I2C_SCL_NORMAL_BUS_SPEED 100000 /* 100KHz I2C */
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#define I2C_SCL_FAST_BUS_SPEED 400000 /* 400KHz I2C */
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#define I2C_RECEIVE 0x01 /* Master receive */
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#define I2C_SEND 0x00 /* Master send */
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/** @} */
|
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/*---------------------------------------------------------------------------*/
|
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/**
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* \name I2C Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Initialize the I2C peripheral and pins
|
||||
* \param port_sda The GPIO number of the pin used fort SDA
|
||||
* \param pin_sda The pin number used for SDA
|
||||
* \param port_scl The GPIO number of the pin used fort SCL
|
||||
* \param pin_scl The pin number used for SCL
|
||||
* \param bus_speed The clock frequency used by I2C module
|
||||
*
|
||||
* \e bus_speed can take the following values:
|
||||
*
|
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* - I2C_SCL_NORMAL_BUS_SPEED : 100KHz
|
||||
* - I2C_SCL_FAST_BUS_SPEED : 400KHz
|
||||
*/
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void i2c_init(uint8_t port_sda, uint8_t pin_sda, uint8_t port_scl,
|
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uint8_t pin_scl, uint32_t bus_speed);
|
||||
|
||||
/** \brief Enable master I2C module */
|
||||
void i2c_master_enable(void);
|
||||
|
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/** \brief Disable master I2C module */
|
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void i2c_master_disable(void);
|
||||
|
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/**
|
||||
* \brief Initialize I2C peripheral clock with given frequency
|
||||
* \param freq The desired frequency
|
||||
*
|
||||
* \e freq can take the following values:
|
||||
*
|
||||
* - I2C_SCL_NORMAL_BUS_SPEED : 100KHz
|
||||
* - I2C_SCL_FAST_BUS_SPEED : 400KHz
|
||||
*/
|
||||
void i2c_set_frequency(uint32_t freq);
|
||||
|
||||
/**
|
||||
* \brief Set the address of slave and access mode for the next I2C communication
|
||||
* \param slave_addr The receiver slave address on 7 bits
|
||||
* \param access_mode The I2C access mode (send/receive)
|
||||
*
|
||||
* \e access_mode can take the following values:
|
||||
*
|
||||
* - I2C_RECEIVE : 1
|
||||
* - I2C_SEND : 0
|
||||
*/
|
||||
void i2c_master_set_slave_address(uint8_t slave_addr, uint8_t access_mode);
|
||||
|
||||
/**
|
||||
* \brief Prepare data to be transmitted
|
||||
* \param data The byte of data to be transmitted from the I2C master
|
||||
*/
|
||||
void i2c_master_data_put(uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Return received data from I2C
|
||||
* \return The byte received by I2C after à receive command
|
||||
*/
|
||||
uint8_t i2c_master_data_get(void);
|
||||
|
||||
/**
|
||||
* \brief Control the state of the master module for send and receive operations
|
||||
* \param cmd The operation to perform
|
||||
*
|
||||
* \e cmd can take the following values:
|
||||
*
|
||||
* - I2C_MASTER_CMD_SINGLE_SEND
|
||||
* - I2C_MASTER_CMD_SINGLE_RECEIVE
|
||||
* - I2C_MASTER_CMD_BURST_SEND_START
|
||||
* - I2C_MASTER_CMD_BURST_SEND_CONT
|
||||
* - I2C_MASTER_CMD_BURST_SEND_FINISH
|
||||
* - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
|
||||
* - I2C_MASTER_CMD_BURST_RECEIVE_START
|
||||
* - I2C_MASTER_CMD_BURST_RECEIVE_CONT
|
||||
* - I2C_MASTER_CMD_BURST_RECEIVE_FINISH
|
||||
* - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
|
||||
*/
|
||||
void i2c_master_command(uint8_t cmd);
|
||||
|
||||
/**
|
||||
* \brief Return the busy state of I2C module
|
||||
* \retval 0 The I2C module is not busy
|
||||
* \retval 1 The I2C module is busy
|
||||
*/
|
||||
uint8_t i2c_master_busy(void);
|
||||
|
||||
/**
|
||||
* \brief Return the status register if error occurred during last communication
|
||||
* \retval I2C_MASTER_ERR_NONE Return 0 if no error occurred
|
||||
*
|
||||
* If an error occurred, return the status register of the I2C module.
|
||||
* Use the result with the I2CM_STAT_* flags to custom your processing
|
||||
*/
|
||||
uint8_t i2c_master_error(void);
|
||||
/**
|
||||
* \brief Perform all operations to send a byte to a slave
|
||||
* \param slave_addr The adress of the slave to which data are sent
|
||||
* \param data The data to send to the slave
|
||||
* \return Return the value of i2c_master_error() after the I2C operation
|
||||
*/
|
||||
uint8_t i2c_single_send(uint8_t slave_addr, uint8_t data);
|
||||
|
||||
/**
|
||||
* \brief Perform all operations to receive a byte from a slave
|
||||
* \param slave_addr The address of the slave from which data are received
|
||||
* \param data A pointer to store the received data
|
||||
* \return Return the value of i2c_master_error() after the I2C operation
|
||||
*/
|
||||
uint8_t i2c_single_receive(uint8_t slave_addr, uint8_t *data);
|
||||
/**
|
||||
* \brief Perform all operations to send multiple bytes to a slave
|
||||
* \param slave_addr The address of the slave to which data are sent
|
||||
* \param data A pointer to the data to send to the slave
|
||||
* \param len Number of bytes to send
|
||||
* \return Return the value of i2c_master_error() after the I2C operation
|
||||
*/
|
||||
uint8_t i2c_burst_send(uint8_t slave_addr, uint8_t *data, uint8_t len);
|
||||
|
||||
/**
|
||||
* \brief Perform all operations to receive multiple bytes from a slave
|
||||
* \param slave_addr The address of the slave from which data are received
|
||||
* \param data A pointer to store the received data
|
||||
* \param len Number of bytes to receive
|
||||
* \return Return the value of i2c_master_error() after the I2C operation
|
||||
*/
|
||||
uint8_t i2c_burst_receive(uint8_t slave_addr, uint8_t *data, uint8_t len);
|
||||
/** @} */
|
||||
|
||||
#endif /* I2C_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
* @}
|
||||
*/
|
Loading…
Reference in a new issue