Merge branch 'master' of git://git.devl.org/git/malvira/libmc1322x
Conflicts: cpu/mc1322x/src/default_lowlevel.c
This commit is contained in:
Mariano Alvira
commit
485d6716e0
331
cpu/mc1322x/lib/i2c.c
Normal file
331
cpu/mc1322x/lib/i2c.c
Normal file
|
|
@ -0,0 +1,331 @@
|
|||
/*
|
||||
* Copyright (c) 2011, Hedde Bosman <heddebosman@incas3.eu>
|
||||
*
|
||||
* I2C communication device drivers for mc1322x
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include "i2c.h"
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
static int8_t tx_byte_ctr;
|
||||
static int8_t rx_byte_ctr;
|
||||
|
||||
static uint8_t* tx_buf_ptr;
|
||||
static uint8_t* rx_buf_ptr;
|
||||
|
||||
|
||||
volatile unsigned int i; // volatile to prevent optimization
|
||||
|
||||
static inline void i2c_send_byte(void) {
|
||||
*I2CDR = *(tx_buf_ptr++); // set new byte, MCF is automatically cleared
|
||||
tx_byte_ctr--;
|
||||
}
|
||||
static inline void i2c_recv_byte(void) {
|
||||
*(rx_buf_ptr++) = *I2CDR;
|
||||
rx_byte_ctr--;
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// void i2c_receiveinit(uint8_t slave_address,
|
||||
// uint8_t prescale)
|
||||
//
|
||||
// This function initializes the USCI module for master-receive operation.
|
||||
//
|
||||
// IN: uint8_t slave_address => Slave Address
|
||||
// uint8_t prescale => SCL clock adjustment
|
||||
//-----------------------------------------------------------------------------
|
||||
//static volatile uint8_t rx_byte_tot = 0;
|
||||
void i2c_receiveinit(uint8_t slave_address, uint8_t byte_ctr, uint8_t *rx_buf) {
|
||||
// wait for bus to be free before setting MSTA (assuming we're in a multi-master environment or still sending something else)
|
||||
while(i2c_busy()) /* wait */;
|
||||
|
||||
// assert: rx_byte_ctr <= 0
|
||||
// assert: tx_byte_ctr <= 0
|
||||
tx_buf_ptr = 0;
|
||||
tx_byte_ctr = 0; // indicate that nothing is to be received
|
||||
rx_byte_ctr = byte_ctr;
|
||||
rx_buf_ptr = rx_buf;
|
||||
|
||||
// clockdiv
|
||||
//*I2CFDR = 0x20; // 150 khz for redbee econotag
|
||||
|
||||
// assume being master, thus no addres has to be set
|
||||
*I2CCR = I2C_MEN |
|
||||
#ifdef I2C_NON_BLOCKING
|
||||
I2C_MIEN |
|
||||
#endif
|
||||
I2C_MSTA | I2C_MTX | I2C_RXAK; // start condition is triggered
|
||||
|
||||
// write out address of slave
|
||||
*I2CDR = (slave_address & 0x7f) <<1 | 0x01;
|
||||
|
||||
#ifndef I2C_NON_BLOCKING
|
||||
i2c_receive();
|
||||
#endif
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// void i2c_transmitinit(uint8_t slave_address,
|
||||
// uint8_t prescale)
|
||||
//
|
||||
// Initializes USCI for master-transmit operation.
|
||||
//
|
||||
// IN: uint8_t slave_address => Slave Address
|
||||
// uint8_t prescale => SCL clock adjustment
|
||||
//------------------------------------------------------------------------------
|
||||
//static volatile uint8_t tx_byte_tot = 0;
|
||||
void i2c_transmitinit(uint8_t slave_address, uint8_t byte_ctr, uint8_t *tx_buf) {
|
||||
// wait for bus to be free before setting MSTA (assuming we're in a multi-master environment or still sending something else)
|
||||
while(i2c_busy()) /* wait */;
|
||||
|
||||
// assert: rx_byte_ctr <= 0
|
||||
// assert: tx_byte_ctr <= 0
|
||||
rx_buf_ptr = 0;
|
||||
rx_byte_ctr = 0; // indicate that nothing is to be received
|
||||
tx_byte_ctr = byte_ctr;
|
||||
tx_buf_ptr = tx_buf;
|
||||
|
||||
// clockdiv
|
||||
//*I2CFDR = 0x20; // 150 khz for redbee econotag
|
||||
|
||||
// assume being master, thus no addres has to be set
|
||||
*I2CCR = I2C_MEN |
|
||||
#ifdef I2C_NON_BLOCKING
|
||||
I2C_MIEN |
|
||||
#endif
|
||||
I2C_MSTA | I2C_MTX ; // start condition is triggered
|
||||
|
||||
// write out address of slave
|
||||
*I2CDR = (slave_address & 0x7f) <<1;
|
||||
|
||||
#ifndef I2C_NON_BLOCKING
|
||||
i2c_transmit();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*- blocking counterparts of interrupt hanlder function ---------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#ifndef I2C_NON_BLOCKING
|
||||
/*----------------------------------------------------------------------------*/
|
||||
uint8_t i2c_receive() {
|
||||
while(rx_byte_ctr > 0) {
|
||||
// busy wait
|
||||
while(!(*I2CSR & I2C_MCF) || !(*I2CSR & I2C_MIF)) /*wait*/;
|
||||
|
||||
if (rx_byte_ctr == 1) { // receiving next-to-last byte, thus turn off auto-ack for stop condition
|
||||
*I2CCR |= I2C_TXAK;
|
||||
}
|
||||
|
||||
if (*I2CSR & I2C_MCF) {
|
||||
i2c_recv_byte(); // read new byte
|
||||
}
|
||||
|
||||
if (*I2CSR & I2C_MAL) {
|
||||
*I2CSR &= ~I2C_MAL; // should be cleared in software
|
||||
printf("*** ERROR I2C: Arbitration lost\n");
|
||||
// Arbitration lost; ERROR?
|
||||
}
|
||||
}
|
||||
|
||||
while(!(*I2CSR & I2C_MCF) || !(*I2CSR & I2C_MIF)) /*wait*/;
|
||||
if (*I2CSR & I2C_RXAK) {
|
||||
// NO acknoledge byte received
|
||||
printf("*** ERROR I2C: No ack received\n");
|
||||
}
|
||||
if (*I2CSR & I2C_MAL) {
|
||||
*I2CSR &= ~I2C_MAL; // should be cleared in software
|
||||
printf("*** ERROR I2C: Arbitration lost\n");
|
||||
// Arbitration lost; ERROR?
|
||||
}
|
||||
|
||||
*I2CCR &= ~I2C_MSTA; // stop condition
|
||||
}
|
||||
/*----------------------------------------------------------------------------*/
|
||||
void i2c_transmit() {
|
||||
while(tx_byte_ctr > 0) {
|
||||
// busy wait
|
||||
while(!(*I2CSR & I2C_MCF) || !(*I2CSR & I2C_MIF)) /*wait*/;
|
||||
|
||||
if (*I2CSR & I2C_RXAK) {
|
||||
// NO acknoledge byte received
|
||||
printf("*** ERROR I2C: No ack received\n");
|
||||
}
|
||||
|
||||
if (*I2CSR & I2C_MCF) {
|
||||
i2c_send_byte();
|
||||
}
|
||||
|
||||
if (*I2CSR & I2C_MAL) {
|
||||
*I2CSR &= ~I2C_MAL; // should be cleared in software
|
||||
printf("*** ERROR I2C: Arbitration lost\n");
|
||||
// Arbitration lost; ERROR?
|
||||
}
|
||||
|
||||
// clear MIF
|
||||
*I2CSR &= ~I2C_MIF;
|
||||
}
|
||||
|
||||
while(!(*I2CSR & I2C_MCF) || !(*I2CSR & I2C_MIF)) /*wait*/;
|
||||
if (*I2CSR & I2C_RXAK) {
|
||||
// NO acknoledge byte received
|
||||
printf("*** ERROR I2C: No ack received\n");
|
||||
}
|
||||
if (*I2CSR & I2C_MAL) {
|
||||
*I2CSR &= ~I2C_MAL; // should be cleared in software
|
||||
printf("*** ERROR I2C: Arbitration lost\n");
|
||||
// Arbitration lost; ERROR?
|
||||
}
|
||||
|
||||
*I2CCR &= ~I2C_MSTA; // stop condition
|
||||
}
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* force SCL to become bus master when sda is still low (can occur after sys reset */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
void i2c_force_reset(void) {
|
||||
uint8_t tmp;
|
||||
*I2CCR = 0x20;
|
||||
*I2CCR = 0xA0;
|
||||
tmp = *I2CDR;
|
||||
// return to module state Master?
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*- check if we're still in the process of sending something ----------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
uint8_t i2c_transferred(void) {
|
||||
return (!i2c_busy() && rx_byte_ctr == 0 && tx_byte_ctr == 0);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* check if there is communication in progress on the i2c bus. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
uint8_t i2c_busy(void) {
|
||||
return ((*I2CSR & I2C_MBB) > 0); // bit 5 high = busy
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Setup ports and pins for I2C use. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
void i2c_enable(void) {
|
||||
// enable clock signal to i2c module
|
||||
*I2CCKER = I2C_CKEN; // enable
|
||||
|
||||
enable_irq(I2C);
|
||||
|
||||
*I2CFDR = 0x20; // clockdiv: 150 khz for redbee econotag
|
||||
*I2CADR = 0x01; // our slave address (not used; we're master)
|
||||
// then enable i2c module
|
||||
*I2CCR |= I2C_MEN | // module-enable, auto-ack = on
|
||||
#ifdef I2C_NON_BLOCKING
|
||||
I2C_MIEN | //module-interrupt-enable
|
||||
#endif
|
||||
0;
|
||||
|
||||
// then switch gpio pins to i2c
|
||||
*GPIO_FUNC_SEL0 |= (0x01 << (I2C_SCL*2)) | (0x01 << (I2C_SDA*2)); // GPIO 12, 13 to i2c
|
||||
// and enable pull-up resistors
|
||||
*GPIO_PAD_PU_EN0 |= (0x01 << I2C_SCL) | (0x01 << I2C_SDA); // Activate internal pull-up/-down resistors
|
||||
*GPIO_PAD_PU_SEL0 |= (0x01 << I2C_SCL) | (0x01 << I2C_SDA); // select pull-up resistors for ports
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Reset ports and pins for GPIO use. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
void i2c_disable(void) {
|
||||
// all control values are set off
|
||||
*I2CCR = 0;
|
||||
// clock is turned off
|
||||
*I2CCKER = ~I2C_CKEN;
|
||||
|
||||
// then switch gpio pins to gpio
|
||||
*GPIO_FUNC_SEL0 &= ~(0x01 << (I2C_SCL*2)) | (0x01 << (I2C_SDA*2)); // GPIO 12, 13 to i2c
|
||||
// and disable resistors
|
||||
*GPIO_PAD_PU_EN0 &= ~(0x01 << I2C_SCL) | (0x01 << I2C_SDA); // Deactivate internal pull-up/-down resistors
|
||||
|
||||
disable_irq(I2C);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/*- i2c interrupt handler --------------------------------------------------*/
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#ifdef I2C_NON_BLOCKING
|
||||
void i2c_isr (void) {
|
||||
uint8_t dummy;
|
||||
if (*I2CSR & I2C_MIF) { // interrupt is from i2c
|
||||
if (*I2CSR & I2C_MCF) { // one byte transferred/received. will be cleared automatically when I2CDR is written or I2CSR read
|
||||
if (tx_buf_ptr != 0) { // we're sending
|
||||
if (*I2CSR & I2C_RXAK) {
|
||||
// NO acknoledge byte received
|
||||
printf("*** ERROR I2C: No ack received\n");
|
||||
}
|
||||
|
||||
if (tx_byte_ctr > 0) { // tx
|
||||
i2c_send_byte(); // set new byte, MCF is automatically cleared
|
||||
} else {
|
||||
*I2CCR &= ~I2C_MSTA; // generate stop condition
|
||||
}
|
||||
} else { //if (rx_buf_ptr != 0) { // receive
|
||||
if (rx_byte_ctr == 1) { // receiving next-to-last byte, thus turn off auto-ack for stop condition
|
||||
*I2CCR |= I2C_TXAK;
|
||||
}
|
||||
if (*I2CCR & I2C_MTX) { // address byte was just sent
|
||||
*I2CCR &= ~I2C_MTX; // switch to receive mode
|
||||
dummy = *I2CDR; // dummy read to throw away the address from register
|
||||
|
||||
} else if (rx_byte_ctr > 0) {
|
||||
i2c_recv_byte(); // read new byte
|
||||
} else {
|
||||
*I2CCR &= ~I2C_MSTA; // generate stop condition
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
if (*I2CSR & I2C_MAL) {
|
||||
*I2CSR &= ~I2C_MAL; // should be cleared in software
|
||||
printf("*** ERROR I2C: Arbitration lost\n");
|
||||
// Arbitration lost; reset..
|
||||
rx_byte_ctr = tx_byte_ctr = 0;
|
||||
*I2CCR &= ~I2C_MSTA; // generate stop condition
|
||||
}
|
||||
|
||||
// clear MIF
|
||||
*I2CSR &= ~I2C_MIF;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
135
cpu/mc1322x/lib/include/i2c.h
Normal file
135
cpu/mc1322x/lib/include/i2c.h
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright (c) 2011, Hedde Bosman <heddebosman@incas3.eu>
|
||||
*
|
||||
* I2C communication device drivers for mc1322x
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the Institute nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef I2C_H
|
||||
#define I2C_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "isr.h"
|
||||
#include "gpio.h"
|
||||
|
||||
#define I2C_NON_BLOCKING 1
|
||||
|
||||
/* The I2C Interrupt Service Routine */
|
||||
void i2c_isr (void);
|
||||
|
||||
/* Enable the I2C module */
|
||||
void i2c_enable(void);
|
||||
|
||||
/* Disable the I2C module */
|
||||
void i2c_disable(void);
|
||||
|
||||
|
||||
|
||||
/* Returns 1 if the I2C bus is active (we or some other device are transferring data) */
|
||||
uint8_t i2c_busy(void);
|
||||
|
||||
/* Returns 1 if our data is sent or received */
|
||||
uint8_t i2c_transferred(void); // indicates success of data last transfer (send or receive)
|
||||
|
||||
|
||||
|
||||
/* start receiving data from 'slave_address' of length 'byte_ctr' and store it in 'rx_buf'
|
||||
* @parameter slave_addr 7bits (and will be padded with the 'receive bit')
|
||||
* @parameter byte_ctr the number of bytes expected to be received
|
||||
* @parameter rx_buf the buffer in which the received bytes will be stored.
|
||||
*
|
||||
* IFDEF I2C_NON_BLOCKING THEN THIS FUNCTION RETURNS IMMEDIATLY BUT THE TRANSFER WILL ONLY
|
||||
* BE COMPLETE WHEN i2c_transferred IS 1
|
||||
*/
|
||||
void i2c_receiveinit( uint8_t slave_address, uint8_t byte_ctr, uint8_t *rx_buf);
|
||||
|
||||
/* start sending data to 'slave_address' of length 'byte_ctr' found in the buffer 'rx_buf'
|
||||
* @parameter slave_addr 7bits (and will be padded with the 'send bit')
|
||||
* @parameter byte_ctr the number of bytes to be sent
|
||||
* @parameter tx_buf the buffer in which the bytes to be sent are stored
|
||||
*
|
||||
* IFDEF I2C_NON_BLOCKING THEN THIS FUNCTION RETURNS IMMEDIATLY BUT THE TRANSFER WILL ONLY
|
||||
* BE COMPLETE WHEN i2c_transferred IS 1
|
||||
*/
|
||||
void i2c_transmitinit(uint8_t slave_address, uint8_t byte_ctr, uint8_t *tx_buf);
|
||||
|
||||
|
||||
#ifndef I2C_NON_BLOCKING
|
||||
#define I2C_NON_BLOCKING 1
|
||||
#endif
|
||||
|
||||
#if I2C_NON_BLOCKING
|
||||
uint8_t i2c_receive(void);
|
||||
void i2c_transmit(void);
|
||||
#endif
|
||||
|
||||
// TODO: see if this is better fit in platform definition
|
||||
#define I2C_SDA 13 //SDA == P5.1 // GPIO 13
|
||||
#define I2C_SCL 12 //SCL == P5.2 // GPIO 12
|
||||
|
||||
// TODO: this could use a nice struct with bit members...
|
||||
|
||||
#define I2C_BASE (0x80006000)
|
||||
|
||||
#define I2CADR ((volatile uint8_t *) ( I2C_BASE + 0x00 ))
|
||||
#define I2CFDR ((volatile uint8_t *) ( I2C_BASE + 0x04 ))
|
||||
#define I2CCR ((volatile uint8_t *) ( I2C_BASE + 0x08 ))
|
||||
#define I2CSR ((volatile uint8_t *) ( I2C_BASE + 0x0C ))
|
||||
#define I2CDR ((volatile uint8_t *) ( I2C_BASE + 0x10 ))
|
||||
#define I2CDFSRR ((volatile uint8_t *) ( I2C_BASE + 0x14 ))
|
||||
#define I2CCKER ((volatile uint8_t *) ( I2C_BASE + 0x18 ))
|
||||
|
||||
// TODO: fix nice structs
|
||||
|
||||
// i2c CR
|
||||
#define I2C_MEN 0x80
|
||||
#define I2C_MIEN 0x40
|
||||
#define I2C_MSTA 0x20
|
||||
#define I2C_MTX 0x10
|
||||
#define I2C_TXAK 0x08
|
||||
#define I2C_RSTA 0x04
|
||||
#define I2C_BCST 0x01
|
||||
|
||||
// i2c SR
|
||||
#define I2C_MCF 0x80
|
||||
#define I2C_MAAS 0x40
|
||||
#define I2C_MBB 0x20
|
||||
#define I2C_MAL 0x10
|
||||
#define I2C_BCSTM 0x08
|
||||
#define I2C_SRW 0x04
|
||||
#define I2C_MIF 0x02
|
||||
#define I2C_RXAK 0x01
|
||||
|
||||
// i2c digital filter sample rate register
|
||||
#define I2C_DFSR 0x3f // default = 0x10
|
||||
|
||||
// i2c CKER
|
||||
#define I2C_CKEN 0x01
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -169,5 +169,6 @@ extern void maca_isr(void) __attribute__((weak));
|
|||
|
||||
extern void asm_isr(void) __attribute__((weak));
|
||||
|
||||
extern void i2c_isr(void) __attribute__((weak));
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -47,5 +47,6 @@
|
|||
#include "uart.h"
|
||||
#include "utils.h"
|
||||
#include "asm.h"
|
||||
#include "i2c.h"
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -83,9 +83,9 @@ void uart1_init(volatile uint16_t inc, volatile uint16_t mod, volatile uint8_t s
|
|||
/* set GPIO15-14 to UART (UART1 TX and RX)*/
|
||||
GPIO->FUNC_SEL.GPIO_14 = 1;
|
||||
GPIO->FUNC_SEL.GPIO_15 = 1;
|
||||
|
||||
|
||||
/* interrupt when there are this number or more bytes free in the TX buffer*/
|
||||
*UART1_UTXCON = 16;
|
||||
UART1->TXCON = 16;
|
||||
u1_tx_head = 0; u1_tx_tail = 0;
|
||||
|
||||
/* enable UART1 interrupts in the interrupt controller */
|
||||
|
|
@ -132,7 +132,7 @@ void uart2_init(volatile uint16_t inc, volatile uint16_t mod, volatile uint8_t s
|
|||
GPIO->FUNC_SEL.GPIO_19 = 1;
|
||||
|
||||
/* interrupt when there are this number or more bytes free in the TX buffer*/
|
||||
*UART2_UTXCON = 16;
|
||||
UART2->TXCON = 16;
|
||||
u2_tx_head = 0; u2_tx_tail = 0;
|
||||
|
||||
/* enable UART2 interrupts in the interrupt controller */
|
||||
|
|
|
|||
|
|
@ -93,6 +93,9 @@ void irq(void)
|
|||
if(bit_is_set(pending, INT_NUM_ASM)) {
|
||||
if(asm_isr != 0) { asm_isr(); }
|
||||
}
|
||||
if (bit_is_set(pending, INT_NUM_I2C)) {
|
||||
if (i2c_isr != 0) { i2c_isr(); }
|
||||
}
|
||||
|
||||
*INTFRC = 0; /* stop forcing interrupts */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue