George Oikonomou
GitHub
commit
4425a67433
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@ -236,6 +236,7 @@
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#define RG_RX_SYN 0x15
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/** Offset for register XAH_CTRL_1 */
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#define RG_XAH_CTRL_1 0x17
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#define SR_AACK_PROM_MODE 0x17, 0x02, 1
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/** Access parameters for sub-register XTAL_MODE in register @ref RG_XOSC_CTRL */
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#define SR_XTAL_MODE 0x12, 0xf0, 4
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/** Access parameters for sub-register XTAL_TRIM in register @ref RG_XOSC_CTRL */
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@ -340,6 +341,7 @@
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#define SR_CSMA_SEED_0 0x2d, 0xff, 0
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/** Offset for register CSMA_SEED_1 */
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#define RG_CSMA_SEED_1 (0x2e)
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#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
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/** Offset for register CSMA_BE */
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#define RG_CSMA_BE 0x2f
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/** Access parameters for sub-register MIN_BE in register @ref RG_CSMA_SEED_1 */
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@ -83,7 +83,10 @@
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#define SR_CCA_DONE 0x141, 0x80, 7
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#define SR_CCA_STATUS 0x141, 0x40, 6
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#define SR_AACK_SET_PD 0x16e, 0x20, 5
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#define SR_AACK_DIS_ACK 0x16e, 0x10, 4
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#define RG_XAH_CTRL_1 (0x157)
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#define SR_AACK_PROM_MODE 0x157, 0x02, 1
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/* RF230 register assignments, for reference */
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#if 0
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@ -41,6 +41,120 @@
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* Registers can be read with a macro, but the args for subregisters don't expand properly so the actual address
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* is used with explicit _SFR_MEM8 in the subregister read/write routines.
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*/
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/* Symbol Counter */
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#define RG_SCCNTHH (0xE4) /* SCCNTHH7-0 */
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#define RG_SCCNTHL (0xE3) /* SCCNTHL7-0 */
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#define RG_SCCNTLH (0xE2) /* SCCNTLH7-0 */
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#define RG_SCCNTLL (0xE1) /* SCCNTLL7-0 */
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/* Counter control register 0 */
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#define RG_SCCR0 (0xdc)
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#define SR_SCCR0 0xdc, 0xff, 0
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#define SR_SCCR0_SCRES 0xdc, 0x80, 7 /* Counter Sync. */
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#define SR_SCCR0_SCMBTS 0xdc, 0x40, 6 /* Manual Beacon timestamp */
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#define SR_SCCR0_SCEN 0xdc, 0x20, 5 /* Counter enable */
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#define SR_SCCR0_SCCKSEL 0xdc, 0x10, 4 /* Counter clock source */
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#define SR_SCCR0_SCTSE 0xdc, 0x08, 3 /* Auto timstamp Beacon, SFD */
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#define SR_SCCR0_SCMP3 0xdc, 0x04, 2 /* Compare 3 counter mode sel. */
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#define SR_SCCR0_SCMP2 0xdc, 0x02, 1 /* Compare 2 counter mode sel. */
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#define SR_SCCR0_SCMP1 0xdc, 0x01, 0 /* Compare 1 counter mode sel. */
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/* Counter control register 1 */
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#define RG_SCCR1 (0xdd)
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#define SR_SCCR1 0xdd, 0xff, 0
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#define SR_SCCR1_SCBTSM 0xdd, 0x20, 5 /* Disable beacon timestamp */
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#define SR_SCCR1_CLKDIV 0xdd, 0x1c, 2 /* CLKDIV */
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#define SR_SCCR1_CLK0 0xdd, 0x10, 4 /* CLK0 */
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#define SR_SCCR1_CLK1 0xdd, 0x08, 3 /* CLK1 */
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#define SR_SCCR1_CLK2 0xdd, 0x04, 2 /* CLK2 */
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#define SR_SCCR1_EECLK 0xdd, 0x02, 1 /* */
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#define SR_SCCR1_SCENBO 0xdd, 0x01, 0 /* Backoff Slot Counter Enable */
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/* Prescaler for symbol counter */
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#define SCCKDIV_62_5k 0
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#define SCCKDIV_125k 1
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#define SCCKDIV_250k 2
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#define SCCKDIV_500k 3
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#define SCCKDIV_1M 4
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#define SCCKDIV_2M 5
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#define SCCKDIV_4M 6
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/* Counter status register 1 */
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#define RG_SCSR (0xde)
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#define SR_SCSR 0xde, 0xff, 0
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#define SR_SCBSY 0xde, 0x01, 0 /* Symbol counter busy */
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/* Counter ISR */
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#define RG_SCIRQS (0xe0)
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#define SR_SCIRQS 0xe0, 0xff, 0
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#define SR_SCIRQS_IRQSB0 0xe0, 0x10, 4 /* Backoff */
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#define SR_SCIRQS_IRQSOF 0xe0, 0x08, 3 /* Counter overflow */
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#define SR_SCIRQS_IRQSCP3 0xe0, 0x04, 2 /* Compare 3 counter */
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#define SR_SCIRQS_IRQSCP2 0xe0, 0x02, 1 /* Compare 2 counter */
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#define SR_SCIRQS_IRQSCP1 0xe0, 0x01, 0 /* Compare 1 counter */
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/* Counter IRQ mask */
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#define RG_SCIRQM (0xdf)
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#define SR_SCIRQM 0xdf, 0xff, 0
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#define SR_SCIRQM_IRQMB0 0xdf, 0x10, 4 /* Backoff mask */
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#define SR_SCIRQM_IRQMOF 0xdf, 0x08, 3 /* Counter overflow mask */
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#define SR_SCIRQM_IRQMCP3 0xdf, 0x04, 2 /* Compare 3 counter mask */
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#define SR_SCIRQM_IRQMCP2 0xdf, 0x02, 1 /* Compare 2 counter mask */
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#define SR_SCIRQM_IRQMCP1 0xdf, 0x01, 0 /* Compare 1 counter mask */
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/* Timestamp SFD */
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#define RG_SCTSRHH 0xFC /* SCTSRHH7-0 */
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#define RG_SCTSRHL 0xFB /* SCTSRHL7-0 */
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#define RG_SCTSRLH 0xFA /* SCTSRLH7-0 */
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#define RG_SCTSRLL 0xF9 /* SCTSRLL7-0 */
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/* Beacon Timestamp */
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#define RG_SCBTSRHH (0xE8) /* SCBTSRHH7-0 */
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#define RG_SCBTSRHL (0xE7) /* SCBTSRHL7-0 */
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#define RG_SCBTSRLH (0xE6) /* SCBTSRLH7-0 */
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#define RG_SCBTSRLL (0xE5) /* SCBTSRLL7-0 */
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/* Output Compare 1 */
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#define RG_SCOCR1HH (0xF8) /* SCOCR1HH7-0 */
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#define RG_SCOCR1HL (0xF7) /* SCOCR1HL7-0 */
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#define RG_SCOCR1LH (0xF6) /* SCOCR1LH7-0 */
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#define RG_SCOCR1LL (0xF5) /* SCOCR1LL7-0 */
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/* Output Compare 2 */
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#define RG_SCOCR2HH (0xF4) /* SCOCR2HH7-0 */
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#define RG_SCOCR2HL (0xF3) /* SCOCR2HL7-0 */
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#define RG_SCOCR2LH (0xF2) /* SCOCR2LH7-0 */
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#define RG_SCOCR2LL (0xF1) /* SCOCR2LL7-0 */
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/* Output Compare 3 */
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#define RG_SCOCR3HH (0xF0) /* SCOCR3HH7-0 */
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#define RG_SCOCR3HL (0xEF) /* SCOCR3HL7-0 */
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#define RG_SCOCR3LH (0xEE) /* SCOCR3LH7-0 */
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#define RG_SCOCR3LL (0xED) /* SCOCR3LL7-0 */
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/* Transmit Frame Timestamp */
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#define RG_SCTSTRHH (0xFC) /* SCTSTRHH7-0 */
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#define RG_SCTSTRHL (0xFB) /* SCTSTRHL7-0 */
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#define RG_SCTSTRLH (0xFA) /* SCTSTRLH7-0 */
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#define RG_SCTSTRLL (0xF9) /* SCTSTRLL7-0 */
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/*
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Interrupt Status
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#define RG_SCIRQS (0xE0) Res2 Res1 Res0 IRQSBO IRQSOF IRQSCP3 IRQSCP2 IRQSCP1 page 173
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Interrupt Mask
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#define RG_SCIRQM (0xDF) Res2 Res1 Res0 IRQMBO IRQMOF IRQMCP3 IRQMCP2 IRQMCP1 page 174
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Counter status
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#define RG_SCSR (0xDE) Res6 Res5 Res4 Res3 Res2 Res1 Res0 SCBSY page 173
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Counter Control 1
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#define RG_SCCR1 (0xDD) Res6 Res5 SCBTSM SCCKDIV2 SCCKDIV1 SCCKDIV0 SCEECLK SCENBO page 172
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Counter Control 0
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#define RG_SCCR0 (0xDC) SCRES SCMBTS SCEN SCCKSEL SCTSE SCCMP3 SCCMP2 SCCMP1 page 171
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Counter Compare Source
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#define RG_SCCSR (0xDB) Res1 Res0 SCCS31 SCCS30 SCCS21 SCCS20 SCCS11 SCCS10 page 161
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*/
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#define RG_TRX_STATUS TRX_STATUS
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#define SR_TRX_STATUS 0x141, 0x1f, 0
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#define SR_TRX_CMD 0x142, 0x1f, 0
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@ -48,9 +162,35 @@
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#define SR_TX_PWR 0x145, 0x0f, 0
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#define RG_VERSION_NUM VERSION_NUM
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#define RG_MAN_ID_0 MAN_ID_0
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#define RG_IRQ_MASK IRQ_MASK
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#define RG_IRQ_MASK (0x14e)
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/** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */
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#define SR_IRQ_MASK 0x14e, 0xff, 0
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/** Offset for register IRQ_STATUS */
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#define RG_IRQ_STATUS (0x14f)
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#define SR_IRQ_STATUS 0x14f, 0xff, 0
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/** Awake Interrupt Status */
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#define SR_IRQ_AWAKE 0x14f, 0x80, 7
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/** TX_END Interrupt Status */
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#define SR_IRQ_TX_END 0x14f, 0x40, 6
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/** Address Match */
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#define SR_IRQ_AMI 0x14f, 0x20, 5
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/** End of ED Measurement Interrupt Status */
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#define SR_CCA_ED_DONE 0x14f, 0x10, 4
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/** Access parameters for sub-register IRQ_3_TRX_END in register @ref RG_IRQ_STATUS */
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#define SR_IRQ_3_TRX_END 0x14f, 0x08, 3
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/** Access parameters for sub-register IRQ_2_RX_START in register @ref RG_IRQ_STATUS */
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#define SR_IRQ_2_RX_START 0x14f, 0x04, 2
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/** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref RG_IRQ_STATUS */
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#define SR_IRQ_1_PLL_UNLOCK 0x14f, 0x02, 1
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/** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref RG_IRQ_STATUS */
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#define RG_XAH_CTRL_1 (0x157)
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#define SR_AACK_PROM_MODE 0x157, 0x02, 1
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#define SR_IRQ_0_PLL_LOCK 0x14f, 0x01, 0
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#define SR_MAX_FRAME_RETRIES 0x16C, 0xf0, 4
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#define SR_TX_AUTO_CRC_ON 0x144, 0x20, 5
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#define SR_PLL_FLT 0x144, 0x10, 4
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#define SR_TRAC_STATUS 0x142, 0xe0, 5
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#define SR_CHANNEL 0x148, 0x1f, 0
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#define SR_CCA_MODE 0x148, 0x60, 5
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@ -67,7 +207,7 @@
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#define RG_IEEE_ADDR_5 IEEE_ADDR_5
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#define RG_IEEE_ADDR_6 IEEE_ADDR_6
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#define RG_IEEE_ADDR_7 IEEE_ADDR_7
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//#define SR_ED_LEVEL 0x147, 0xff, 0
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/* #define SR_ED_LEVEL 0x147, 0xff, 0 */
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#define RG_PHY_ED_LEVEL PHY_ED_LEVEL
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#define RG_RX_SYN RX_SYN
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#define SR_RSSI 0x146, 0x1f, 0
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@ -81,12 +221,13 @@
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#define RG_CSMA_BE CSMA_BE
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#define RG_CSMA_SEED_0 CSMA_SEED_0
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#define RG_PHY_RSSI PHY_RSSI
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//#define SR_CCA_CS_THRES 0x149, 0xf0, 4
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#define SR_CCA_CS_THRES 0x149, 0xf0, 4
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#define SR_CCA_ED_THRES 0x149, 0x0f, 0
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#define SR_CCA_DONE 0x141, 0x80, 7
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#define SR_CCA_STATUS 0x141, 0x40, 6
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#define SR_AACK_SET_PD 0x16e, 0x20, 5
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#define SR_CSMA_SEED_1 0x16e, 0x10, 4
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#define SR_CSMA_SEED_1 0x16e, 0x03, 0
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#define SR_AACK_DIS_ACK 0x16e, 0x10, 4
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/* RF230 register assignments, for reference */
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#if 1
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@ -216,27 +357,6 @@
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///** Access parameters for sub-register CCA_ED_THRES in register @ref RG_CCA_THRES */
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//#define SR_CCA_ED_THRES 0x09, 0x0f, 0
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///** Offset for register IRQ_MASK */
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//#define RG_IRQ_MASK (0x0e)
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///** Access parameters for sub-register IRQ_MASK in register @ref RG_IRQ_MASK */
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//#define SR_IRQ_MASK 0x0e, 0xff, 0
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///** Offset for register IRQ_STATUS */
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//#define RG_IRQ_STATUS (0x0f)
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///** Access parameters for sub-register IRQ_7_BAT_LOW in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
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///** Access parameters for sub-register IRQ_6_TRX_UR in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
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///** Access parameters for sub-register IRQ_5 in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_5 0x0f, 0x20, 5
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///** Access parameters for sub-register IRQ_4 in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_4 0x0f, 0x10, 4
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///** Access parameters for sub-register IRQ_3_TRX_END in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
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///** Access parameters for sub-register IRQ_2_RX_START in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
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///** Access parameters for sub-register IRQ_1_PLL_UNLOCK in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
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///** Access parameters for sub-register IRQ_0_PLL_LOCK in register @ref RG_IRQ_STATUS */
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//#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
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///** Offset for register VREG_CTRL */
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//#define RG_VREG_CTRL (0x10)
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///** Access parameters for sub-register AVREG_EXT in register @ref RG_VREG_CTRL */
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@ -94,6 +94,9 @@
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static bool is_promiscuous;
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#endif
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/* Poll mode disabled by default */
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uint8_t poll_mode = 0;
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/* RF230_CONF_FRAME_RETRIES is 1 plus the number written to the hardware. */
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/* Valid range 1-16, zero disables extended mode. */
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#ifndef RF230_CONF_FRAME_RETRIES
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@ -201,6 +204,8 @@ extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
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#define DEBUGFLOW(c)
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#endif
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static radio_status_t radio_set_trx_state(uint8_t new_state);
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/* XXX hack: these will be made as Chameleon packet attributes */
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#if RF230_CONF_TIMESTAMPS
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rtimer_clock_t rf230_time_of_arrival, rf230_time_of_departure;
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@ -254,17 +259,186 @@ static int rf230_cca(void);
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uint8_t rf230_last_correlation,rf230_last_rssi,rf230_smallest_rssi;
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static void
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set_poll_mode(bool enable)
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{
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poll_mode = enable;
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if(poll_mode) {
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rf230_set_rpc(0x0); /* Disbable all RPC features */
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radio_set_trx_state(RX_ON);
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hal_subregister_write(SR_IRQ_MASK, RF230_SUPPORTED_INTERRUPT_MASK);
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/* hal_register_write(RG_IRQ_MASK, 0xFF); */
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} else {
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/* Initialize and enable interrupts */
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rf230_set_rpc(0xFF); /* Enable all RPC features. Only XRFR2 radios */
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radio_set_trx_state(RX_AACK_ON);
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}
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}
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static bool
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get_poll_mode(void)
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{
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return poll_mode;
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}
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void
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set_frame_filtering(bool i)
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{
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if(i)
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hal_subregister_write(SR_AACK_PROM_MODE, 0);
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else {
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hal_subregister_write(SR_AACK_PROM_MODE, 1);
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}
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}
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static bool
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get_frame_filtering(void)
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{
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int i = hal_subregister_read(SR_AACK_PROM_MODE);
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if(i)
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return 0;
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return 1;
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}
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void
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set_auto_ack(bool i)
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{
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if(i)
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hal_subregister_write(SR_AACK_DIS_ACK, 0);
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else
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hal_subregister_write(SR_AACK_DIS_ACK, 1);
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}
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static bool
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get_auto_ack(void)
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{
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int i = hal_subregister_read(SR_AACK_DIS_ACK);
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if(i)
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return 0;
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return 1;
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}
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/*---------------------------------------------------------------------------*/
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static radio_result_t
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get_value(radio_param_t param, radio_value_t *value)
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{
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return RADIO_RESULT_NOT_SUPPORTED;
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if(!value) {
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return RADIO_RESULT_INVALID_VALUE;
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}
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switch(param) {
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case RADIO_PARAM_POWER_MODE:
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/* *value = (REG(RFCORE_XREG_RXENABLE) && RFCORE_XREG_RXENABLE_RXENMASK) == 0 )?
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RADIO_POWER_MODE_OFF : RADIO_POWER_MODE_ON; */
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return RADIO_RESULT_OK;
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case RADIO_PARAM_TX_MODE:
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return RADIO_RESULT_OK;
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case RADIO_PARAM_CHANNEL:
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*value = (radio_value_t)rf230_get_channel();
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return RADIO_RESULT_OK;
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case RADIO_PARAM_PAN_ID:
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/* *value = get_pan_id(); */
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return RADIO_RESULT_OK;
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case RADIO_PARAM_16BIT_ADDR:
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/* *value = get_short_addr(); */
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return RADIO_RESULT_OK;
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case RADIO_PARAM_RX_MODE:
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*value = 0;
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if(get_frame_filtering()) {
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*value |= RADIO_RX_MODE_ADDRESS_FILTER;
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}
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if(get_auto_ack()) {
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*value |= RADIO_RX_MODE_AUTOACK;
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}
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if(get_poll_mode()) {
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*value |= RADIO_RX_MODE_POLL_MODE;
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}
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return RADIO_RESULT_OK;
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case RADIO_PARAM_TXPOWER:
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*value = rf230_get_txpower();
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return RADIO_RESULT_OK;
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case RADIO_PARAM_CCA_THRESHOLD:
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/* *value = get_cca_threshold(); */
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return RADIO_RESULT_OK;
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case RADIO_PARAM_RSSI:
|
||||
*value = rf230_get_raw_rssi();
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_CONST_CHANNEL_MIN:
|
||||
*value = RF230_MIN_CHANNEL;
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_CONST_CHANNEL_MAX:
|
||||
*value = RF230_MAX_CHANNEL;;
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_CONST_TXPOWER_MIN:
|
||||
*value = TX_PWR_MIN;
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_CONST_TXPOWER_MAX:
|
||||
*value = TX_PWR_MAX;
|
||||
return RADIO_RESULT_OK;
|
||||
default:
|
||||
return RADIO_RESULT_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static radio_result_t
|
||||
set_value(radio_param_t param, radio_value_t value)
|
||||
{
|
||||
return RADIO_RESULT_NOT_SUPPORTED;
|
||||
switch(param) {
|
||||
case RADIO_PARAM_POWER_MODE:
|
||||
if(value == RADIO_POWER_MODE_ON) {
|
||||
rf230_on();
|
||||
return RADIO_RESULT_OK;
|
||||
}
|
||||
if(value == RADIO_POWER_MODE_OFF) {
|
||||
rf230_off();
|
||||
return RADIO_RESULT_OK;
|
||||
}
|
||||
return RADIO_RESULT_INVALID_VALUE;
|
||||
|
||||
case RADIO_PARAM_CHANNEL:
|
||||
|
||||
if(value < RF230_MIN_CHANNEL ||
|
||||
value > RF230_MAX_CHANNEL) {
|
||||
return RADIO_RESULT_INVALID_VALUE;
|
||||
}
|
||||
|
||||
rf230_set_channel(value);
|
||||
return RADIO_RESULT_OK;
|
||||
|
||||
case RADIO_PARAM_TX_MODE:
|
||||
return RADIO_RESULT_OK;
|
||||
|
||||
case RADIO_PARAM_PAN_ID:
|
||||
/* set_pan_id(value & 0xffff); */
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_PARAM_16BIT_ADDR:
|
||||
/* set_short_addr(value & 0xffff); */
|
||||
return RADIO_RESULT_OK;
|
||||
case RADIO_PARAM_RX_MODE:
|
||||
|
||||
if(value & ~(RADIO_RX_MODE_ADDRESS_FILTER | RADIO_RX_MODE_POLL_MODE |
|
||||
RADIO_RX_MODE_AUTOACK)) {
|
||||
return RADIO_RESULT_INVALID_VALUE;
|
||||
}
|
||||
set_frame_filtering((value & RADIO_RX_MODE_ADDRESS_FILTER) != 0);
|
||||
set_auto_ack((value & RADIO_RX_MODE_AUTOACK) != 0);
|
||||
set_poll_mode((value & RADIO_RX_MODE_POLL_MODE) != 0);
|
||||
return RADIO_RESULT_OK;
|
||||
|
||||
case RADIO_PARAM_TXPOWER:
|
||||
if(value < TX_PWR_MIN || value > TX_PWR_MAX) {
|
||||
return RADIO_RESULT_INVALID_VALUE;
|
||||
}
|
||||
rf230_set_txpower(value);
|
||||
return RADIO_RESULT_OK;
|
||||
|
||||
case RADIO_PARAM_CCA_THRESHOLD:
|
||||
/* set_cca_threshold(value); */
|
||||
return RADIO_RESULT_OK;
|
||||
default:
|
||||
return RADIO_RESULT_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
static radio_result_t
|
||||
|
|
@ -347,7 +521,7 @@ hal_rx_frame_t rxframe[RF230_CONF_RX_BUFFERS];
|
|||
* \retval STATE_TRANSITION The radio transceiver's state machine is in
|
||||
* transition between two states.
|
||||
*/
|
||||
//static uint8_t
|
||||
|
||||
uint8_t
|
||||
radio_get_trx_state(void)
|
||||
{
|
||||
|
|
@ -878,7 +1052,7 @@ void rf230_warm_reset(void) {
|
|||
DDRB &= ~(1<<7);
|
||||
#endif
|
||||
|
||||
hal_register_write(RG_IRQ_MASK, RF230_SUPPORTED_INTERRUPT_MASK);
|
||||
hal_subregister_write(SR_IRQ_MASK, RF230_SUPPORTED_INTERRUPT_MASK);
|
||||
|
||||
/* Set up number of automatic retries 0-15
|
||||
* (0 implies PLL_ON sends instead of the extended TX_ARET mode */
|
||||
|
|
|
|||
Loading…
Reference in a new issue