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Added energy estimation, embryo for possible future drift configuration

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adamdunkels 2007-05-22 20:59:47 +00:00
parent 9a5bac6282
commit 432d242a3c
1 changed files with 21 additions and 11 deletions
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32
cpu/msp430/rtimer-arch.c
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@ -28,7 +28,7 @@
* *
* This file is part of the Contiki operating system. * This file is part of the Contiki operating system.
* *
* $Id: rtimer-arch.c,v 1.3 2007/04/07 05:45:08 adamdunkels Exp $ * $Id: rtimer-arch.c,v 1.4 2007/05/22 20:59:47 adamdunkels Exp $
*/ */
/** /**
@ -41,6 +41,7 @@
#include <io.h> #include <io.h>
#include <signal.h> #include <signal.h>
#include "lib/energest.h"
#include "sys/rtimer.h" #include "sys/rtimer.h"
#define DEBUG 0 #define DEBUG 0
@ -51,11 +52,15 @@
#define PRINTF(...) #define PRINTF(...)
#endif #endif
static rtimer_clock_t offset;
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
interrupt(TIMERB1_VECTOR) timerb1 (void) { interrupt(TIMERB1_VECTOR) timerb1 (void) {
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(TBIV == 2) { if(TBIV == 2) {
rtimer_run_next(); rtimer_run_next();
} }
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
void void
@ -63,19 +68,18 @@ rtimer_arch_init(void)
{ {
dint(); dint();
/* Select SMCLK (2.4576MHz), clear TAR */ offset = 0;
/* TACTL = TASSEL1 | TACLR | ID_3; */
/* Select SMCLK (2.4576MHz), clear TAR; This makes the rtimer count
the number of processor cycles executed by the CPU. */
//TBCTL = TBSSEL1 | TBCLR;
/* Select ACLK 32768Hz clock, divide by 8 */ /* Select ACLK 32768Hz clock, divide by 8 */
TBCTL = TBSSEL0 | TBCLR | ID_3; TBCTL = TBSSEL0 | TBCLR | ID_3;
/* Initialize ccr1 to create the X ms interval. */
/* CCR1 interrupt enabled, interrupt occurs when timer equals CCR1. */ /* CCR1 interrupt enabled, interrupt occurs when timer equals CCR1. */
TBCCTL1 = CCIE; TBCCTL1 = CCIE;
/* Interrupt after X ms. */ /* Start Timer_B in continuous mode. */
/* TBCCR1 = INTERVAL;*/
/* Start Timer_A in continuous mode. */
TBCTL |= MC1; TBCTL |= MC1;
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */ BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
@ -88,12 +92,18 @@ void
rtimer_arch_schedule(rtimer_clock_t t) rtimer_arch_schedule(rtimer_clock_t t)
{ {
PRINTF("rtimer_arch_schedule time %u\n", t); PRINTF("rtimer_arch_schedule time %u\n", t);
TBCCR1 = t; TBCCR1 = t + offset;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
rtimer_clock_t /*rtimer_clock_t
rtimer_arch_now(void) rtimer_arch_now(void)
{ {
return TBR; return TBR + offset;
}*/
/*---------------------------------------------------------------------------*/
void
rtimer_arch_set(rtimer_clock_t t)
{
offset = t - TBR;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/