initial try at init entry execution
This commit is contained in:
parent
99c91d7e3e
commit
424761f23d
6
Makefile
6
Makefile
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@ -60,9 +60,9 @@ ALL = $(TESTS:.c=.srec) $(TESTS:.c=.bin) $(TESTS:.c=.dis)
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all: src/start.o $(ALL)
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all: src/start.o $(ALL)
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tests/nvm-read.obj: src/maca.o
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tests/nvm-read.obj: src/maca.o src/nvm.o
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tests/rftest-rx.obj: src/maca.o
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tests/rftest-rx.obj: src/maca.o src/nvm.o
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tests/rftest-tx.obj: src/maca.o
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tests/rftest-tx.obj: src/maca.o src/nvm.o
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%.srec: %.obj
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%.srec: %.obj
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$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
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$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
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@ -5422,8 +5422,10 @@ Disassembly of section P2:
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4031c6: 2900 cmp r1, #0
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4031c6: 2900 cmp r1, #0
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4031c8: d1fb bne.n 4031c2 <SMAC_InitExecuteEntry+0x1e>
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4031c8: d1fb bne.n 4031c2 <SMAC_InitExecuteEntry+0x1e>
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4031ca: e7f2 b.n 4031b2 <SMAC_InitExecuteEntry+0xe>
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4031ca: e7f2 b.n 4031b2 <SMAC_InitExecuteEntry+0xe>
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4031cc: 2901 cmp r1, #1 // at this point r1 is between 1 and 15 inclusive
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4031cc: 2901 cmp r1, #1 // 3: at this point r1 is between 1 and 15 inclusive
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4031ce: d118 bne.n 403202 <SMAC_InitExecuteEntry+0x5e> // if !=1 return
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4031ce: d118 bne.n 403202 <SMAC_InitExecuteEntry+0x5e> // if !=1 return
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4031e2: 2004 movs r0, #4 // return 4 bytes processed
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4031e4: 4770 bx lr
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0x00000001 command
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0x00000001 command
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0xaaaaaaaa
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0xaaaaaaaa
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@ -5445,8 +5447,6 @@ if (buf[0] == 0x00000001) {
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*buf[2] = (*buf[2] & ~buf[1]) | (buf[3] & buf[1]);
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*buf[2] = (*buf[2] & ~buf[1]) | (buf[3] & buf[1]);
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}
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}
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4031e2: 2004 movs r0, #4 // return 4 bytes processed
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4031e4: 4770 bx lr
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4031e6: 4a09 ldr r2, [pc, #36] (40320c <SMAC_InitExecuteEntry+0x68>) //2: r2=0x0000fff1
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4031e6: 4a09 ldr r2, [pc, #36] (40320c <SMAC_InitExecuteEntry+0x68>) //2: r2=0x0000fff1
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4031e8: 4291 cmp r1, r2 // r1 >=16
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4031e8: 4291 cmp r1, r2 // r1 >=16
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4031ea: d20a bcs.n 403202 <SMAC_InitExecuteEntry+0x5e> // if r1 >= 0xfff1 then return 0
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4031ea: d20a bcs.n 403202 <SMAC_InitExecuteEntry+0x5e> // if r1 >= 0xfff1 then return 0
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@ -5460,7 +5460,7 @@ if (buf[0] == 0x00000001) {
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4031fa: 4a06 ldr r2, [pc, #24] (403214 <SMAC_InitExecuteEntry+0x70>) r2 = &u8RamValues
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4031fa: 4a06 ldr r2, [pc, #24] (403214 <SMAC_InitExecuteEntry+0x70>) r2 = &u8RamValues
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4031fc: 6800 ldr r0, [r0, #0] // r0 = next value in buffer 2nd half of pair
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4031fc: 6800 ldr r0, [r0, #0] // r0 = next value in buffer 2nd half of pair
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4031fe: 5450 strb r0, [r2, r1] // store this in u8RamValues
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4031fe: 5450 strb r0, [r2, r1] // store this in u8RamValues
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403200: e7d7 b.n 4031b2 <SMAC_InitExecuteEntry+0xe>
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403200: e7d7 b.n 4031b2 <SMAC_InitExecuteEntry+0xe> // return 2
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403202: 2000 movs r0, #0 // return 0
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403202: 2000 movs r0, #0 // return 0
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403204: 4770 bx lr
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403204: 4770 bx lr
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403206: 46c0 nop (mov r8, r8)
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403206: 46c0 nop (mov r8, r8)
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@ -397,6 +397,7 @@ typedef union maca_maskirq_reg_tag
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uint32_t Reg;
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uint32_t Reg;
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} maca_maskirq_reg_t;
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} maca_maskirq_reg_t;
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#define _is_action_complete_interrupt(x) (0 != (maca_irq_acpl & x))
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#define _is_action_complete_interrupt(x) (0 != (maca_irq_acpl & x))
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#define _is_filter_failed_interrupt(x) (0 != (maca_irq_flt & x))
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#define _is_filter_failed_interrupt(x) (0 != (maca_irq_flt & x))
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@ -1,6 +1,8 @@
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#ifndef NVM_H
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#ifndef NVM_H
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#define NVM_H
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#define NVM_H
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#include "embedded_types.h"
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typedef enum
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typedef enum
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{
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{
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gNvmType_NoNvm_c,
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gNvmType_NoNvm_c,
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@ -34,7 +36,7 @@ typedef enum
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/* ROM code seems to be THUMB */
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/* ROM code seems to be THUMB */
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/* need to be in a THUMB block before calling them */
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/* need to be in a THUMB block before calling them */
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volatile nvmErr_t (*nvm_detect)(nvmInterface_t nvmInterface,nvmType_t* pNvmType) = 0x00006cb9;
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extern volatile nvmErr_t (*nvm_detect)(nvmInterface_t nvmInterface,nvmType_t* pNvmType);
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volatile nvmErr_t (*nvm_read)(nvmInterface_t nvmInterface , nvmType_t nvmType , void *pDest, uint32_t address, uint32_t numBytes) = 0x00006d69;
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extern volatile nvmErr_t (*nvm_read)(nvmInterface_t nvmInterface , nvmType_t nvmType , void *pDest, uint32_t address, uint32_t numBytes);
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volatile void(*nvm_setsvar)(uint32_t zero_for_awesome) = 0x00007085;
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extern volatile void(*nvm_setsvar)(uint32_t zero_for_awesome);
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#endif //NVM_H
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#endif //NVM_H
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63
src/maca.c
63
src/maca.c
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@ -1,8 +1,11 @@
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#include "embedded_types.h"
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#include "embedded_types.h"
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#include "maca.h"
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#include "maca.h"
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#include "nvm.h"
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#define reg(x) (*(volatile uint32_t *)(x))
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#define reg(x) (*(volatile uint32_t *)(x))
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static uint8_t ram_values[4];
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void init_phy(void)
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void init_phy(void)
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{
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{
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volatile uint32_t cnt;
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volatile uint32_t cnt;
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@ -347,6 +350,66 @@ void set_channel(uint8_t chan) {
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/* duh! */
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/* duh! */
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}
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}
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#define ROM_END 0x0013ffff
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#define ENTRY_EOF 0x00000e0f
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/* processes up to 4 words of initialization entries */
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/* returns the number of words processed */
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uint8_t exec_init_entry(uint32_t *entries, uint8_t *valbuf)
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{
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volatile uint32_t i;
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if(entries[0] <= ROM_END) {
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if (entries[0] == 0) {
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/* do delay command*/
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for(i=0; i<entries[1]; i++) { continue; }
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return 2;
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} else if (entries[0] == 1) {
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/* do bit set/clear command*/
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reg(entries[2]) = (reg(entries[2]) & ~entries[1]) | (entries[3] & entries[1]);
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return 4;
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} else if ((entries[0] >= 16) &&
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(entries[0] < 0xfff1)) {
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/* store bytes in valbuf */
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valbuf[(entries[0]>>4)-1] = entries[1];
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return 2;
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} else if (entries[0] == ENTRY_EOF) {
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return 0;
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} else {
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/* invalid command code */
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return 0;
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}
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} else { /* address isn't in ROM space */
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/* do store value in address command */
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reg(entries[0]) = entries[1];
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return 2;
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}
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}
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#define FLASH_INIT_MAGIC 0x00000abc
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uint32_t init_from_flash(uint32_t addr) {
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nvmType_t type=0;
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nvmErr_t err;
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uint32_t buf[4];
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uint16_t len;
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uint32_t i=0;
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err = nvm_detect(gNvmInternalInterface_c, &type);
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nvm_setsvar(0);
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err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr, 8);
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i+=8;
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if(buf[0] == FLASH_INIT_MAGIC) {
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len = buf[1] & 0x0000ffff;
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while(i<len) {
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err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr+i, 32);
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i += exec_init_entry(buf, ram_values);
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}
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return i;
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} else {
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return 0;
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}
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}
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/*
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/*
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* Do the ABORT-Wait-NOP-Wait sequence in order to prevent MACA malfunctioning.
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* Do the ABORT-Wait-NOP-Wait sequence in order to prevent MACA malfunctioning.
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* This seqeunce is synchronous and no interrupts should be triggered when it is done.
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* This seqeunce is synchronous and no interrupts should be triggered when it is done.
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