galileo: Add support for Gen. 1 pinmux and GPIO
This patch adds support for IO pinmuxing and GPIO on first generation Intel Galileo boards.master-31012017
Michael LeMay
parent
b17a936bf7
commit
4181179985
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@ -5,7 +5,17 @@ LIBGCC_PATH = /usr/lib/gcc/$(shell gcc -dumpmachine)/$(shell gcc -dumpversion)
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CONTIKI_TARGET_DIRS = . core/sys/ drivers/ net/
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CONTIKI_TARGET_MAIN = ${addprefix $(OBJECTDIR)/,contiki-main.o}
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CONTIKI_SOURCEFILES += contiki-main.c clock.c rtimer-arch.c gpio-pcal9535a.c pwm-pca9685.c galileo-pinmux.c eth-proc.c eth-conf.c galileo-gpio.c
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CONTIKI_SOURCEFILES += contiki-main.c clock.c rtimer-arch.c eth-proc.c eth-conf.c galileo-gpio.c
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GALILEO_GEN ?= 2
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CFLAGS += -DGALILEO_GEN=$(GALILEO_GEN)
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CONTIKI_SOURCEFILES += galileo-gen$(GALILEO_GEN)-pinmux.c
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ifeq ($(GALILEO_GEN),2)
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CONTIKI_SOURCEFILES += gpio-pcal9535a.c pwm-pca9685.c
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else
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CONTIKI_SOURCEFILES += cy8c9540a.c
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endif
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ifeq ($(CONTIKI_WITH_IPV6),1)
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CONTIKI_SOURCEFILES += nbr-table.c packetbuf.c linkaddr.c link-stats.c
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@ -141,6 +141,9 @@ specify X86_CONF_RESTRICT_DMA=1 as a command-line argument to the make
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command that is used to build the image. This will configure and lock
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the IMRs.
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Galileo Gen. 2 is targeted by default. Specify GALILEO_GEN=1 on the build
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command line to target first generation boards.
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Running
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-------
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@ -193,7 +196,8 @@ $ cp examples/hello-world/hello-world.galileo.efi /mnt/sdcard/efi/boot/bootia32.
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### Connect to the console output
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Connect the serial cable to your computer as shown in [2].
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Connect the serial cable to your computer as shown in [8] for first generation
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boards and [2] for second generation boards.
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Choose a terminal emulator such as PuTTY. Make sure you use the SCO keyboard
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mode (on PuTTY that option is at Terminal -> Keyboard, on the left menu).
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@ -277,3 +281,5 @@ References
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[6] https://docs.docker.com/docker-for-windows/#/shared-drives
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[7] https://docs.docker.com/engine/understanding-docker/
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[8] https://software.intel.com/en-us/articles/intel-galileo-gen-1-board-assembly-using-eclipse-and-intel-xdk-iot-edition
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@ -0,0 +1,131 @@
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/*
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cy8c9540a.h"
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#include <assert.h>
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#include "i2c.h"
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#include <stdio.h>
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/* Change this to 0x21 if J2 is set to 1-2
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* (covering the pin marked with the white triangle). */
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#define I2C_ADDR 0x20
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#define REG_PORT_SEL 0x18
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#define REG_PORT_DIR 0x1C
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#define PORT_CNT 6
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/* Cache the current state of each port to obviate the need for reading before
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* writing to output ports when simply updating a single pin.
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*/
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static uint8_t out_cache[PORT_CNT];
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/*---------------------------------------------------------------------------*/
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static void
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write_reg(uint8_t reg, uint8_t data)
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{
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uint8_t pkt[] = { reg, data };
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assert(quarkX1000_i2c_polling_write(pkt, sizeof(pkt), I2C_ADDR) == 0);
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}
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/*---------------------------------------------------------------------------*/
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static uint8_t
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read_reg(uint8_t reg)
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{
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uint8_t data;
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assert(quarkX1000_i2c_polling_write(®, 1, I2C_ADDR) == 0);
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assert(quarkX1000_i2c_polling_read(&data, 1, I2C_ADDR) == 0);
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return data;
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}
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/*---------------------------------------------------------------------------*/
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void
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cy8c9540a_init(void)
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{
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uint8_t status;
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/* has to init after I2C master */
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assert(quarkX1000_i2c_is_available());
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status = read_reg(0x2E);
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if((status >> 4) != 4) {
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fprintf(stderr, "Failed to communicate with CY8C9540A. Perhaps jumper J2 "
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"is not set to 2-3? Halting.\n");
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halt();
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}
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set the direction (in or out) for the indicated GPIO pin.
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*/
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void
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cy8c9540a_set_port_dir(cy8c9540a_bit_addr_t addr, cy8c9540a_port_dir_t dir)
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{
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uint8_t mask;
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assert(addr.port < PORT_CNT);
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write_reg(REG_PORT_SEL, addr.port);
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mask = read_reg(REG_PORT_DIR);
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mask &= ~(1 << addr.pin);
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mask |= ((uint8_t)dir) << addr.pin;
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write_reg(REG_PORT_DIR, mask);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set the drive mode for the indicated GPIO pin.
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*/
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void
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cy8c9540a_set_drive_mode(cy8c9540a_bit_addr_t addr,
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cy8c9540a_drive_mode_t drv_mode)
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{
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assert(addr.port < PORT_CNT);
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write_reg(REG_PORT_SEL, addr.port);
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write_reg((uint8_t)drv_mode, 1 << addr.pin);
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}
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/*---------------------------------------------------------------------------*/
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bool
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cy8c9540a_read(cy8c9540a_bit_addr_t addr)
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{
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assert(addr.port < PORT_CNT);
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return ((read_reg(addr.port) >> addr.pin) & 1) == 1;
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}
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/*---------------------------------------------------------------------------*/
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void
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cy8c9540a_write(cy8c9540a_bit_addr_t addr, bool val)
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{
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assert(addr.port < PORT_CNT);
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out_cache[addr.port] &= ~(1 << addr.pin);
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out_cache[addr.port] |= ((uint8_t)val) << addr.pin;
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write_reg(8 + addr.port, out_cache[addr.port]);
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}
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/*---------------------------------------------------------------------------*/
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@ -0,0 +1,72 @@
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/*
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_
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#define PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_
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#include <stdbool.h>
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#include <stdint.h>
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/* Driver for Cypress Semiconductors CY8C9540A device used for GPIO, PWM, and
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* pinmuxing on the first generation Intel Galileo.
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*/
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/* The numeric value of each drive mode corresponds to the device register
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* address for selecting that mode. Only a subset of the available modes are
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* listed here.
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*/
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typedef enum cy8c9540a_drive_mode {
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CY8C9540A_DRIVE_PULL_UP = 0x1D,
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CY8C9540A_DRIVE_PULL_DOWN = 0x1E,
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CY8C9540A_DRIVE_STRONG = 0x21,
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CY8C9540A_DRIVE_HI_Z = 0x23
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} cy8c9540a_drive_mode_t;
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typedef enum cy8c9540a_port_dir {
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CY8C9540A_PORT_DIR_OUT = 0,
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CY8C9540A_PORT_DIR_IN = 1
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} cy8c9540a_port_dir_t;
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typedef struct cy8c9540a_bit_addr {
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uint8_t port;
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int pin;
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} cy8c9540a_bit_addr_t;
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#define CY8C9540A_BIT_ADDR_INVALID_PORT 0xFF
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void cy8c9540a_init(void);
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void cy8c9540a_set_port_dir(cy8c9540a_bit_addr_t addr,
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cy8c9540a_port_dir_t dir);
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void cy8c9540a_set_drive_mode(cy8c9540a_bit_addr_t addr,
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cy8c9540a_drive_mode_t drv_mode);
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bool cy8c9540a_read(cy8c9540a_bit_addr_t addr);
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void cy8c9540a_write(cy8c9540a_bit_addr_t addr, bool val);
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#endif /* PLATFORM_GALILEO_DRIVERS_CY8C9540A_H_ */
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@ -0,0 +1,282 @@
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/*
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* Copyright (C) 2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "galileo-pinmux.h"
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#include <assert.h>
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#include "cy8c9540a.h"
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#include "gpio.h"
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#include <stdio.h>
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static cy8c9540a_bit_addr_t mux_bit_addrs[] = {
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{ 3, 4 }, /* IO0 */
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{ 3, 5 }, /* IO1 */
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{ 1, 7 }, /* IO2 */
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{ 1, 6 }, /* IO3 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO4 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO5 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO6 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO7 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO8 */
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 }, /* IO9 */
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{ 3, 6 }, /* IO10 */
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{ 3, 7 }, /* IO11 */
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{ 5, 2 }, /* IO12 */
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{ 5, 3 }, /* IO13 */
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{ 3, 1 }, /* A0 */
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{ 3, 0 }, /* A1 */
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{ 0, 7 }, /* A2 */
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{ 0, 6 }, /* A3 */
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{ 0, 5 }, /* A4 (also controlled by I2C mux) */
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{ 0, 4 }, /* A5 (also controlled by I2C mux) */
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};
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static cy8c9540a_bit_addr_t i2c_mux_bit_addr = { 1, 5 };
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/*---------------------------------------------------------------------------*/
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static void
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flatten_pin_num(galileo_pin_group_t grp, unsigned *pin)
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{
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if(grp == GALILEO_PIN_GRP_ANALOG) {
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*pin += GALILEO_NUM_DIGITAL_PINS;
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}
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assert(*pin < GALILEO_NUM_PINS);
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}
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/*---------------------------------------------------------------------------*/
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/* See galileo-gpio.c for the declaration of this function. */
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int
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galileo_brd_to_cpu_gpio_pin(unsigned pin, bool *sus)
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{
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assert(pin < GALILEO_NUM_PINS);
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*sus = false;
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switch(pin) {
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case 2:
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return 6;
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case 3:
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return 7;
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case 10:
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return 2;
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default:
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return -1; /* GPIO pin may be connected to the CY8C9540A chip, but not the
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CPU. */
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}
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}
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/*---------------------------------------------------------------------------*/
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static cy8c9540a_bit_addr_t cy8c9540a_gpio_mapping[] = {
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{ 4, 6 },
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{ 4, 7 },
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 },
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{ CY8C9540A_BIT_ADDR_INVALID_PORT, 0 },
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{ 1, 4 },
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{ 0, 1 },
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{ 1, 0 },
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{ 1, 3 },
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{ 1, 2 },
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{ 0, 3 },
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{ 0, 0 }, /* This driver configures IO10 to connect to CPU GPIO when setting
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IO10 to a digital mode, but hardware exists to alternately
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connect it to this pin of the CY8C9540A chip. */
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{ 1, 1 },
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{ 3, 2 },
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{ 3, 3 },
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{ 4, 0 },
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{ 4, 1 },
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{ 4, 2 },
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{ 4, 3 },
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{ 4, 4 },
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{ 4, 5 }
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};
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/* Map a board-level GPIO pin number to the address of the CY8C9540A pin that
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* implements it.
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*/
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cy8c9540a_bit_addr_t
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galileo_brd_to_cy8c9540a_gpio_pin(unsigned pin)
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{
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assert(pin < GALILEO_NUM_PINS);
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return cy8c9540a_gpio_mapping[pin];
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}
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/*---------------------------------------------------------------------------*/
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/* The I2C mux control must be set high to be able to access A4 and A5.
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*/
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static void
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set_i2c_mux(bool val)
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{
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cy8c9540a_write(i2c_mux_bit_addr, val);
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}
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/*---------------------------------------------------------------------------*/
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static void
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select_gpio_pwm(unsigned flat_pin, bool pwm)
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{
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bool mux_val;
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cy8c9540a_bit_addr_t mux_bit_addr;
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mux_bit_addr = mux_bit_addrs[flat_pin];
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if(mux_bit_addr.port != CY8C9540A_BIT_ADDR_INVALID_PORT) {
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mux_val = pwm || !(flat_pin == 2 || flat_pin == 3 || flat_pin == 10);
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cy8c9540a_write(mux_bit_addr, mux_val);
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}
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if((GALILEO_NUM_DIGITAL_PINS + 4) <= flat_pin) {
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/* This single control switches away from both I2C pins. */
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set_i2c_mux(true);
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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select_gpio(galileo_pin_group_t grp, unsigned pin, bool out)
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{
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bool sus;
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int cpu_pin;
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cy8c9540a_bit_addr_t gpio_bit_addr;
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flatten_pin_num(grp, &pin);
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select_gpio_pwm(pin, false);
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cpu_pin = galileo_brd_to_cpu_gpio_pin(pin, &sus);
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if(cpu_pin == -1) {
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gpio_bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
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cy8c9540a_set_port_dir(gpio_bit_addr,
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out?
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CY8C9540A_PORT_DIR_OUT :
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CY8C9540A_PORT_DIR_IN);
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cy8c9540a_set_drive_mode(gpio_bit_addr,
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out?
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CY8C9540A_DRIVE_STRONG :
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CY8C9540A_DRIVE_HI_Z);
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} else {
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quarkX1000_gpio_config(cpu_pin,
|
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out? QUARKX1000_GPIO_OUT : QUARKX1000_GPIO_IN);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void
|
||||
galileo_pinmux_select_din(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
select_gpio(grp, pin, false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_dout(galileo_pin_group_t grp, unsigned pin)
|
||||
{
|
||||
select_gpio(grp, pin, true);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_pwm(unsigned pin)
|
||||
{
|
||||
switch(pin) {
|
||||
case 3:
|
||||
case 5:
|
||||
case 6:
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "%s: invalid pin: %d.\n", __FUNCTION__, pin);
|
||||
halt();
|
||||
}
|
||||
|
||||
select_gpio_pwm(pin, true);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_serial(unsigned pin)
|
||||
{
|
||||
assert(pin == 0 || pin == 1);
|
||||
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_i2c(void)
|
||||
{
|
||||
set_i2c_mux(false);
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_spi(void)
|
||||
{
|
||||
unsigned pin;
|
||||
for(pin = 11; pin <= 13; pin++) {
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
void galileo_pinmux_select_analog(unsigned pin)
|
||||
{
|
||||
assert(pin < GALILEO_NUM_ANALOG_PINS);
|
||||
pin += GALILEO_NUM_DIGITAL_PINS;
|
||||
|
||||
cy8c9540a_write(mux_bit_addrs[pin], false);
|
||||
|
||||
if(4 <= pin) {
|
||||
/* This single control switches away from both I2C pins. */
|
||||
set_i2c_mux(true);
|
||||
}
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
int
|
||||
galileo_pinmux_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
cy8c9540a_init();
|
||||
|
||||
/* Configure all mux control pins as outputs. */
|
||||
for(i = 0; i < GALILEO_NUM_PINS; i++) {
|
||||
if(mux_bit_addrs[i].port == CY8C9540A_BIT_ADDR_INVALID_PORT) {
|
||||
continue;
|
||||
}
|
||||
|
||||
cy8c9540a_set_port_dir(mux_bit_addrs[i], CY8C9540A_PORT_DIR_OUT);
|
||||
cy8c9540a_set_drive_mode(mux_bit_addrs[i], CY8C9540A_DRIVE_STRONG);
|
||||
}
|
||||
cy8c9540a_set_port_dir(i2c_mux_bit_addr, CY8C9540A_PORT_DIR_OUT);
|
||||
cy8c9540a_set_drive_mode(i2c_mux_bit_addr, CY8C9540A_DRIVE_STRONG);
|
||||
|
||||
/* Activate default pinmux configuration. */
|
||||
galileo_pinmux_select_serial(0);
|
||||
galileo_pinmux_select_serial(1);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 2);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 3);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 4);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 5);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 6);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 7);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 8);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 9);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 10);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 11);
|
||||
galileo_pinmux_select_dout(GALILEO_PIN_GRP_DIGITAL, 12);
|
||||
galileo_pinmux_select_din(GALILEO_PIN_GRP_DIGITAL, 13);
|
||||
galileo_pinmux_select_analog(0);
|
||||
galileo_pinmux_select_analog(1);
|
||||
galileo_pinmux_select_analog(2);
|
||||
galileo_pinmux_select_analog(3);
|
||||
galileo_pinmux_select_i2c();
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
|
@ -31,14 +31,22 @@
|
|||
#include "galileo-gpio.h"
|
||||
#include <assert.h>
|
||||
#include "gpio.h"
|
||||
#if GALILEO_GEN == 1
|
||||
#include "cy8c9540a.h"
|
||||
#endif
|
||||
|
||||
/* Must be implemented in board-specific pinmux file to map a board-level GPIO
|
||||
* pin number to the corresponding CPU GPIO pin number.
|
||||
*
|
||||
* The return value should always be a positive number. An assertion within the
|
||||
* For gen. 1 boards, the value -1 may be returned to indicate that the
|
||||
* specified GPIO pin is not connected to any CPU pin. For gen. 2 boards, the
|
||||
* return value should always be a positive number. An assertion within the
|
||||
* function should check the validity of the pin number.
|
||||
*/
|
||||
int galileo_brd_to_cpu_gpio_pin(unsigned pin, bool *sus);
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t galileo_brd_to_cy8c9540a_gpio_pin(unsigned pin);
|
||||
#endif
|
||||
|
||||
static int
|
||||
brd_to_cpu_pin(unsigned pin)
|
||||
|
|
@ -63,10 +71,32 @@ void galileo_gpio_config(uint8_t pin, int flags)
|
|||
*/
|
||||
void galileo_gpio_read(uint8_t pin, uint8_t *value)
|
||||
{
|
||||
assert(quarkX1000_gpio_read(brd_to_cpu_pin(pin), value) == 0);
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t bit_addr;
|
||||
#endif
|
||||
int cpu_pin = brd_to_cpu_pin(pin);
|
||||
#if GALILEO_GEN == 1
|
||||
if(cpu_pin == -1) {
|
||||
bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
|
||||
*value = cy8c9540a_read(bit_addr);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
assert(quarkX1000_gpio_read(cpu_pin, value) == 0);
|
||||
}
|
||||
|
||||
void galileo_gpio_write(uint8_t pin, uint8_t value)
|
||||
{
|
||||
assert(quarkX1000_gpio_write(brd_to_cpu_pin(pin), value) == 0);
|
||||
#if GALILEO_GEN == 1
|
||||
cy8c9540a_bit_addr_t bit_addr;
|
||||
#endif
|
||||
int cpu_pin = brd_to_cpu_pin(pin);
|
||||
#if GALILEO_GEN == 1
|
||||
if(cpu_pin == -1) {
|
||||
bit_addr = galileo_brd_to_cy8c9540a_gpio_pin(pin);
|
||||
cy8c9540a_write(bit_addr, value);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
assert(quarkX1000_gpio_write(cpu_pin, value) == 0);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue