do2unix conversion
This commit is contained in:
nvt-se
parent
30f5e29db7
commit
4003c3a8c9
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@ -1,94 +1,94 @@
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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#define HAVE_STDINT_H
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#include "msp430def.h"
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#define WITH_SD 0
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#define NETSTACK_CONF_RADIO cc1020_driver
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#define NETSTACK_CONF_RDC lpp_driver
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#define NETSTACK_CONF_MAC csma_driver
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#define NETSTACK_CONF_NETWORK rime_driver
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#define NETSTACK_CONF_FRAMER framer_nullmac
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#define MAC_CONF_CHANNEL_CHECK_RATE 8
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#define ENERGEST_CONF_ON 1
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#define IRQ_PORT1 0x01
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#define IRQ_PORT2 0x02
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#define IRQ_ADC 0x03
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/* MSP430 information memory */
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#define INFOMEM_START 0x1000
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#define INFOMEM_BLOCK_SIZE 128
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#define INFOMEM_NODE_ID 0x0000 /* - 0x0004 */
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#define CC_CONF_REGISTER_ARGS 1
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#define CC_CONF_FUNCTION_POINTER_ARGS 1
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#define CC_CONF_INLINE inline
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#define CC_CONF_VA_ARGS 1
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#define LPP_CONF_LISTEN_TIME 2
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#define LPP_CONF_OFF_TIME (CLOCK_SECOND - (LPP_CONF_LISTEN_TIME))
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#define QUEUEBUF_CONF_NUM 4
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#define CCIF
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#define CLIF
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/* Clear channel assessment timeout for sending with the CC1020 radio. (ms) */
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#define CC1020_CONF_CCA_TIMEOUT 10
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/* Clock */
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typedef unsigned clock_time_t;
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#define CLOCK_CONF_SECOND 64
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#define F_CPU 2457600uL /* CPU target speed in Hz. */
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#define BAUD2UBR(baud) (F_CPU/(baud))
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#include "ctk/ctk-vncarch.h"
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#define LOG_CONF_ENABLED 0
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/**
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* The statistics data type.
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*
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* This datatype determines how high the statistics counters are able
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* to count.
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*/
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typedef uint16_t uip_stats_t;
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typedef int bool;
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#define TRUE 1
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#define FALSE 0
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#define UIP_CONF_ICMP_DEST_UNREACH 1
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#define UIP_CONF_DHCP_LIGHT
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_BUFFER_SIZE 116
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#define UIP_CONF_RECEIVE_WINDOW (UIP_CONF_BUFFER_SIZE - 40)
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#define UIP_CONF_MAX_CONNECTIONS 4
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#define UIP_CONF_MAX_LISTENPORTS 8
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#define UIP_CONF_UDP_CONNS 8
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#define UIP_CONF_FWCACHE_SIZE 20
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#define UIP_CONF_BROADCAST 1
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#define UIP_ARCH_IPCHKSUM 1
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#define UIP_CONF_UDP_CHECKSUMS 1
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#define UIP_CONF_PINGADDRCONF 0
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#define UIP_CONF_LOGGING 0
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#define LOADER_CONF_ARCH "loader/loader-arch.h"
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#define ELFLOADER_CONF_DATAMEMORY_SIZE 100
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x1000
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/* LEDs ports MSB430 */
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x80
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#define LEDS_CONF_GREEN 0x00
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#define LEDS_CONF_YELLOW 0x00
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#endif /* !CONTIKI_CONF_H */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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#define HAVE_STDINT_H
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#include "msp430def.h"
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#define WITH_SD 0
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#define NETSTACK_CONF_RADIO cc1020_driver
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#define NETSTACK_CONF_RDC lpp_driver
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#define NETSTACK_CONF_MAC csma_driver
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#define NETSTACK_CONF_NETWORK rime_driver
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#define NETSTACK_CONF_FRAMER framer_nullmac
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#define MAC_CONF_CHANNEL_CHECK_RATE 8
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#define ENERGEST_CONF_ON 1
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#define IRQ_PORT1 0x01
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#define IRQ_PORT2 0x02
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#define IRQ_ADC 0x03
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/* MSP430 information memory */
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#define INFOMEM_START 0x1000
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#define INFOMEM_BLOCK_SIZE 128
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#define INFOMEM_NODE_ID 0x0000 /* - 0x0004 */
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#define CC_CONF_REGISTER_ARGS 1
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#define CC_CONF_FUNCTION_POINTER_ARGS 1
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#define CC_CONF_INLINE inline
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#define CC_CONF_VA_ARGS 1
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#define LPP_CONF_LISTEN_TIME 2
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#define LPP_CONF_OFF_TIME (CLOCK_SECOND - (LPP_CONF_LISTEN_TIME))
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#define QUEUEBUF_CONF_NUM 4
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#define CCIF
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#define CLIF
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/* Clear channel assessment timeout for sending with the CC1020 radio. (ms) */
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#define CC1020_CONF_CCA_TIMEOUT 10
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/* Clock */
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typedef unsigned clock_time_t;
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#define CLOCK_CONF_SECOND 64
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#define F_CPU 2457600uL /* CPU target speed in Hz. */
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#define BAUD2UBR(baud) (F_CPU/(baud))
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#include "ctk/ctk-vncarch.h"
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#define LOG_CONF_ENABLED 0
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/**
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* The statistics data type.
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*
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* This datatype determines how high the statistics counters are able
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* to count.
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*/
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typedef uint16_t uip_stats_t;
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typedef int bool;
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#define TRUE 1
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#define FALSE 0
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#define UIP_CONF_ICMP_DEST_UNREACH 1
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#define UIP_CONF_DHCP_LIGHT
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#define UIP_CONF_LLH_LEN 0
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#define UIP_CONF_BUFFER_SIZE 116
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#define UIP_CONF_RECEIVE_WINDOW (UIP_CONF_BUFFER_SIZE - 40)
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#define UIP_CONF_MAX_CONNECTIONS 4
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#define UIP_CONF_MAX_LISTENPORTS 8
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#define UIP_CONF_UDP_CONNS 8
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#define UIP_CONF_FWCACHE_SIZE 20
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#define UIP_CONF_BROADCAST 1
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#define UIP_ARCH_IPCHKSUM 1
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#define UIP_CONF_UDP_CHECKSUMS 1
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#define UIP_CONF_PINGADDRCONF 0
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#define UIP_CONF_LOGGING 0
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#define LOADER_CONF_ARCH "loader/loader-arch.h"
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#define ELFLOADER_CONF_DATAMEMORY_SIZE 100
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#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x1000
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/* LEDs ports MSB430 */
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#define LEDS_PxDIR P5DIR
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#define LEDS_PxOUT P5OUT
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#define LEDS_CONF_RED 0x80
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#define LEDS_CONF_GREEN 0x00
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#define LEDS_CONF_YELLOW 0x00
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#endif /* !CONTIKI_CONF_H */
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@ -1,263 +1,263 @@
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#ifndef CC1020_INTERNAL_H
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#define CC1020_INTERNAL_H
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#include <signal.h>
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#define CC1020_MAIN 0x00
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#define CC1020_INTERFACE 0x01
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#define CC1020_RESET 0x02
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#define CC1020_SEQUENCING 0x03
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#define CC1020_FREQ_2A 0x04
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#define CC1020_FREQ_1A 0x05
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#define CC1020_FREQ_0A 0x06
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#define CC1020_CLOCK_A 0x07
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#define CC1020_FREQ_2B 0x08
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#define CC1020_FREQ_1B 0x09
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#define CC1020_FREQ_0B 0x0A
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#define CC1020_CLOCK_B 0x0B
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#define CC1020_VCO 0x0C
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#define CC1020_MODEM 0x0D
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#define CC1020_DEVIATION 0x0E
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#define CC1020_AFC_CONTROL 0x0F
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#define CC1020_FILTER 0x10
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#define CC1020_VGA1 0x11
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#define CC1020_VGA2 0x12
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#define CC1020_VGA3 0x13
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#define CC1020_VGA4 0x14
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#define CC1020_LOCK 0x15
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#define CC1020_FRONTEND 0x16
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#define CC1020_ANALOG 0x17
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#define CC1020_BUFF_SWING 0x18
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#define CC1020_BUFF_CURRENT 0x19
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#define CC1020_PLL_BW 0x1A
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#define CC1020_CALIBRATE 0x1B
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#define CC1020_PA_POWER 0x1C
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#define CC1020_MATCH 0x1D
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#define CC1020_PHASE_COMP 0x1E
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#define CC1020_GAIN_COMP 0x1F
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#define CC1020_POWERDOWN 0x20
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#define CC1020_TEST1 0x21
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#define CC1020_TEST2 0x22
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#define CC1020_TEST3 0x23
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#define CC1020_TEST4 0x24
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#define CC1020_TEST5 0x25
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#define CC1020_TEST6 0x26
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#define CC1020_TEST7 0x27
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#define CC1020_STATUS 0x40
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#define CC1020_RESET_DONE 0x41
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#define CC1020_RSS 0x42
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#define CC1020_AFC 0x43
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#define CC1020_GAUSS_FILTER 0x44
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#define CC1020_STATUS1 0x45
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#define CC1020_STATUS2 0x46
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#define CC1020_STATUS3 0x47
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#define CC1020_STATUS4 0x48
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#define CC1020_STATUS5 0x49
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#define CC1020_STATUS6 0x4A
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#define CC1020_STATUS7 0x4B
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/* Flags for the MAIN register. */
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#define RESET_N 1
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#define BIAS_PD (1<<1)
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#define XOSC_PD (1<<2)
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#define FS_PD (1<<3)
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#define PD_MODE_1 (1<<4)
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#define PD_MODE_2 (1<<5)
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#define F_REG (1<<6)
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#define RXTX (1<<7)
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/* In power up mode, the MAIN register modifies some flags to the following. */
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#define SEQ_PD (1<<1)
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#define SEQ_CAL_1 (1<<2)
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#define SEQ_CAL_2 (1<<3)
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// For CC1020_STATUS
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#define CARRIER_SENSE 0x08
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#define LOCK_CONTINUOUS 0x10
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#define LOCK_INSTANT 0x20
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#define SEQ_ERROR 0x40
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#define CAL_COMPLETE 0x80
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#define PA_POWER 0x0F // initial default for output power
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#define LOCK_NOK 0x00
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#define LOCK_OK 0x01
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#define LOCK_RECAL_OK 0x02
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#define CAL_TIMEOUT 0x7FFE
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#define LOCK_TIMEOUT 0x7FFE
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#define RESET_TIMEOUT 0x7FFE
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#define TX_CURRENT 0x87
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#define RX_CURRENT 0x86
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// CC1020 driver configuration
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// PDI (Data in) is on P21
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#define PDO (P2IN & 0x01)
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// PSEL is on P30 and low active
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#define PSEL_ON do { P3OUT &= ~0x01; } while(0)
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#define PSEL_OFF do { P3OUT |= 0x01; } while(0)
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#define PCLK_HIGH do { P2OUT |= 0x08; } while(0)
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#define PCLK_LOW do { P2OUT &= ~0x08; } while(0)
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// PDO (Data out) is on P22
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#define PDI_HIGH do { P2OUT |= 0x02; } while(0)
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#define PDI_LOW do { P2OUT &= ~0x02; } while(0)
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// Enable power for LNA (P24, low-active)
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#define LNA_POWER_ON() do { P2OUT &= ~0x10; } while(0)
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#define LNA_POWER_OFF() do { P2OUT |= 0x10; } while(0)
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#define CC_LOCK (P2IN & 0x04)
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#define DISABLE_RX_IRQ() \
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do { IE1 &= ~(URXIE0); } while(0)
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#define ENABLE_RX_IRQ() \
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do { IFG1 &= ~URXIFG0; IE1 |= URXIE0; } while(0)
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#define ACK_TIMEOUT_115 4 // In RADIO_STROKE ticks
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#define ACK_TIMEOUT_19 16
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#define MHZ_869525 1
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const uint8_t cc1020_config_19200[41] = {
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0x01, // 0x00, MAIN
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0x0F, // 0x01, INTERFACE
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0xFF, // 0x02, RESET
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0x8F, // 0x03, SEQUENCING
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// 869.525 at 50kHz
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0x3A, // 0x04, FREQ_2A
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0x32, // 0x05, FREQ_1A
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0x97, // 0x06, FREQ_0A // 19200
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0x38, // 0x07, CLOCK_A // 19200
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0x3A, // 0x08, FREQ_2B
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0x37, // 0x09, FREQ_1B
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0xEB, // 0x0A, FREQ_0B // 19200
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0x38, // 0x0B, CLOCK_B // 19200
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0x44, // 0x0C, VCO 44
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0x51, // 0x0D, MODEM Manchester
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0x2B, // 0x0E, DEVIATION // FSK
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0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
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0x25, // 0x10, FILTER Bandwith 51.2 kHz i.e. channel spacing 100kHz
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0x61, // 0x11, VGA1
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0x55, // 0x12, VGA2
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0x2D, // 0x13, VGA3
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0x37, // 0x14, VGA4 // 0x29, VGA4 ADJUSTED CS to 23!
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0x40, // 0x15, LOCK is Carrier SENSE
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0x76, // 0x16, FRONTEND
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0x87, // 0x17, ANALOG, RX=86/TX=87
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0x10, // 0x18, BUFF_SWING
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0x25, // 0x19, BUFF_CURRENT
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0xAE, // 0x1A, PLL_BW
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0x34, // 0x1B, CALIBRATE
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PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
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0xF0, // 0x1D, MATCH
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0x00, // 0x1E, PHASE_COMP
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0x00, // 0x1F, GAIN_COMP
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0x00, // 0x20, POWERDOWN
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0x4d, // 0x4d, // 0x21,
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0x10, // 0x10, // 0x22,
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0x06, // 0x06, // 0x23,
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0x00, // 0x00, // 0x24,
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0x40, // 0x40, // 0x25,
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0x00, // 0x00, // 0x26,
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0x00, // 0x00, // 0x27,
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// Not in real config of chipCon from here!!!
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ACK_TIMEOUT_19
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};
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const uint8_t cc1020_config_115200[41] = {
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0x01, // 0x00, MAIN
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0x0F, // 0x01, INTERFACE
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0xFF, // 0x02, RESET
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0x8F, // 0x03, SEQUENCING
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// 869.525 at 200kHz
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0x3A, // 0x04, FREQ_2A
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0x32, // 0x05, FREQ_1A
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0x97, // 0x06, FREQ_0A // 19200
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0x29, // 0x07, CLOCK_A // 19200
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0x3A, // 0x08, FREQ_2B
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0x37, // 0x09, FREQ_1B
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0xEB, // 0x0A, FREQ_0B // 19200
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0x29, // 0x0B, CLOCK_B // 19200
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0x44, // 0x0C, VCO 44
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0x51, // 0x0D, MODEM Manchester
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0x58, // 0x0E, DEVIATION // FSK
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0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
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0x80, // 0x10, FILTER Bandwith 307.2kHz, i.e. channel spacing 500 kHz
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0x61, // 0x11, VGA1
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0x57, // 0x12, VGA2
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0x30, // 0x13, VGA3
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0x35, // 0x14, VGA4
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0x20, // 0x15, LOCK is Carrier SENSE
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0x76, // 0x16, FRONTEND
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0x87, // 0x17, ANALOG, RX=86/TX=87
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0x10, // 0x18, BUFF_SWING
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0x25, // 0x19, BUFF_CURRENT
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0xAE, // 0x1A, PLL_BW
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0x34, // 0x1B, CALIBRATE
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PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
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0xF0, // 0x1D, MATCH
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0x00, // 0x1E, PHASE_COMP
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0x00, // 0x1F, GAIN_COMP
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0x00, // 0x20, POWERDOWN
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0x4d, // 0x21,
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0x10, // 0x22,
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0x06, // 0x23,
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0x00, // 0x24,
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0x40, // 0x25,
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0x00, // 0x26,
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0x00, // 0x27,
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// Not in real config of chipCon from here!!!
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ACK_TIMEOUT_115
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};
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/// cc1020 state
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enum cc1020_state {
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CC1020_OFF = 0,
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CC1020_RX = 0x01,
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CC1020_TX = 0x02,
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CC1020_RX_SEARCHING = 0x10, // searching for preamble + sync word
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CC1020_RX_RECEIVING = 0x20, // receiving bytes
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CC1020_RX_PROCESSING = 0x40, // processing data in buffer
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CC1020_OP_STATE = 0x73,
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CC1020_TURN_OFF = 0x80,
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};
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#define CC1020_SET_OPSTATE(opstate) cc1020_state = ((cc1020_state & ~CC1020_OP_STATE) | (opstate))
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/******************************************************************************
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* @name Packet specification
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* @{
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*/
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// header: number of bytes in packet including header
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struct cc1020_header {
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uint8_t pad;
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uint8_t length;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
#define CC1020_BUFFERSIZE 128
|
||||
|
||||
|
||||
#define PREAMBLE_SIZE 6
|
||||
#define PREAMBLE 0xAA
|
||||
|
||||
#define SYNCWORD_SIZE 2
|
||||
#define HDR_SIZE (sizeof (struct cc1020_header))
|
||||
|
||||
#define CRC_SIZE 2
|
||||
|
||||
#define TAIL_SIZE 2
|
||||
#define TAIL 0xFA
|
||||
|
||||
|
||||
///@}
|
||||
|
||||
#endif /* CC1020_INTERNAL_H */
|
||||
#ifndef CC1020_INTERNAL_H
|
||||
#define CC1020_INTERNAL_H
|
||||
|
||||
#include <signal.h>
|
||||
|
||||
#define CC1020_MAIN 0x00
|
||||
#define CC1020_INTERFACE 0x01
|
||||
#define CC1020_RESET 0x02
|
||||
#define CC1020_SEQUENCING 0x03
|
||||
#define CC1020_FREQ_2A 0x04
|
||||
#define CC1020_FREQ_1A 0x05
|
||||
#define CC1020_FREQ_0A 0x06
|
||||
#define CC1020_CLOCK_A 0x07
|
||||
#define CC1020_FREQ_2B 0x08
|
||||
#define CC1020_FREQ_1B 0x09
|
||||
#define CC1020_FREQ_0B 0x0A
|
||||
#define CC1020_CLOCK_B 0x0B
|
||||
#define CC1020_VCO 0x0C
|
||||
#define CC1020_MODEM 0x0D
|
||||
#define CC1020_DEVIATION 0x0E
|
||||
#define CC1020_AFC_CONTROL 0x0F
|
||||
#define CC1020_FILTER 0x10
|
||||
#define CC1020_VGA1 0x11
|
||||
#define CC1020_VGA2 0x12
|
||||
#define CC1020_VGA3 0x13
|
||||
#define CC1020_VGA4 0x14
|
||||
#define CC1020_LOCK 0x15
|
||||
#define CC1020_FRONTEND 0x16
|
||||
#define CC1020_ANALOG 0x17
|
||||
#define CC1020_BUFF_SWING 0x18
|
||||
#define CC1020_BUFF_CURRENT 0x19
|
||||
#define CC1020_PLL_BW 0x1A
|
||||
#define CC1020_CALIBRATE 0x1B
|
||||
#define CC1020_PA_POWER 0x1C
|
||||
#define CC1020_MATCH 0x1D
|
||||
#define CC1020_PHASE_COMP 0x1E
|
||||
#define CC1020_GAIN_COMP 0x1F
|
||||
#define CC1020_POWERDOWN 0x20
|
||||
#define CC1020_TEST1 0x21
|
||||
#define CC1020_TEST2 0x22
|
||||
#define CC1020_TEST3 0x23
|
||||
#define CC1020_TEST4 0x24
|
||||
#define CC1020_TEST5 0x25
|
||||
#define CC1020_TEST6 0x26
|
||||
#define CC1020_TEST7 0x27
|
||||
#define CC1020_STATUS 0x40
|
||||
#define CC1020_RESET_DONE 0x41
|
||||
#define CC1020_RSS 0x42
|
||||
#define CC1020_AFC 0x43
|
||||
#define CC1020_GAUSS_FILTER 0x44
|
||||
#define CC1020_STATUS1 0x45
|
||||
#define CC1020_STATUS2 0x46
|
||||
#define CC1020_STATUS3 0x47
|
||||
#define CC1020_STATUS4 0x48
|
||||
#define CC1020_STATUS5 0x49
|
||||
#define CC1020_STATUS6 0x4A
|
||||
#define CC1020_STATUS7 0x4B
|
||||
|
||||
/* Flags for the MAIN register. */
|
||||
#define RESET_N 1
|
||||
#define BIAS_PD (1<<1)
|
||||
#define XOSC_PD (1<<2)
|
||||
#define FS_PD (1<<3)
|
||||
#define PD_MODE_1 (1<<4)
|
||||
#define PD_MODE_2 (1<<5)
|
||||
#define F_REG (1<<6)
|
||||
#define RXTX (1<<7)
|
||||
|
||||
/* In power up mode, the MAIN register modifies some flags to the following. */
|
||||
#define SEQ_PD (1<<1)
|
||||
#define SEQ_CAL_1 (1<<2)
|
||||
#define SEQ_CAL_2 (1<<3)
|
||||
|
||||
// For CC1020_STATUS
|
||||
#define CARRIER_SENSE 0x08
|
||||
#define LOCK_CONTINUOUS 0x10
|
||||
#define LOCK_INSTANT 0x20
|
||||
#define SEQ_ERROR 0x40
|
||||
#define CAL_COMPLETE 0x80
|
||||
|
||||
#define PA_POWER 0x0F // initial default for output power
|
||||
#define LOCK_NOK 0x00
|
||||
#define LOCK_OK 0x01
|
||||
#define LOCK_RECAL_OK 0x02
|
||||
#define CAL_TIMEOUT 0x7FFE
|
||||
#define LOCK_TIMEOUT 0x7FFE
|
||||
#define RESET_TIMEOUT 0x7FFE
|
||||
#define TX_CURRENT 0x87
|
||||
#define RX_CURRENT 0x86
|
||||
|
||||
// CC1020 driver configuration
|
||||
|
||||
// PDI (Data in) is on P21
|
||||
#define PDO (P2IN & 0x01)
|
||||
|
||||
// PSEL is on P30 and low active
|
||||
#define PSEL_ON do { P3OUT &= ~0x01; } while(0)
|
||||
#define PSEL_OFF do { P3OUT |= 0x01; } while(0)
|
||||
#define PCLK_HIGH do { P2OUT |= 0x08; } while(0)
|
||||
#define PCLK_LOW do { P2OUT &= ~0x08; } while(0)
|
||||
|
||||
// PDO (Data out) is on P22
|
||||
#define PDI_HIGH do { P2OUT |= 0x02; } while(0)
|
||||
|
||||
#define PDI_LOW do { P2OUT &= ~0x02; } while(0)
|
||||
|
||||
// Enable power for LNA (P24, low-active)
|
||||
#define LNA_POWER_ON() do { P2OUT &= ~0x10; } while(0)
|
||||
|
||||
#define LNA_POWER_OFF() do { P2OUT |= 0x10; } while(0)
|
||||
|
||||
#define CC_LOCK (P2IN & 0x04)
|
||||
|
||||
#define DISABLE_RX_IRQ() \
|
||||
do { IE1 &= ~(URXIE0); } while(0)
|
||||
|
||||
#define ENABLE_RX_IRQ() \
|
||||
do { IFG1 &= ~URXIFG0; IE1 |= URXIE0; } while(0)
|
||||
|
||||
#define ACK_TIMEOUT_115 4 // In RADIO_STROKE ticks
|
||||
#define ACK_TIMEOUT_19 16
|
||||
|
||||
#define MHZ_869525 1
|
||||
|
||||
const uint8_t cc1020_config_19200[41] = {
|
||||
0x01, // 0x00, MAIN
|
||||
0x0F, // 0x01, INTERFACE
|
||||
0xFF, // 0x02, RESET
|
||||
0x8F, // 0x03, SEQUENCING
|
||||
// 869.525 at 50kHz
|
||||
0x3A, // 0x04, FREQ_2A
|
||||
0x32, // 0x05, FREQ_1A
|
||||
0x97, // 0x06, FREQ_0A // 19200
|
||||
0x38, // 0x07, CLOCK_A // 19200
|
||||
0x3A, // 0x08, FREQ_2B
|
||||
0x37, // 0x09, FREQ_1B
|
||||
0xEB, // 0x0A, FREQ_0B // 19200
|
||||
0x38, // 0x0B, CLOCK_B // 19200
|
||||
0x44, // 0x0C, VCO 44
|
||||
0x51, // 0x0D, MODEM Manchester
|
||||
0x2B, // 0x0E, DEVIATION // FSK
|
||||
0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
|
||||
0x25, // 0x10, FILTER Bandwith 51.2 kHz i.e. channel spacing 100kHz
|
||||
0x61, // 0x11, VGA1
|
||||
0x55, // 0x12, VGA2
|
||||
0x2D, // 0x13, VGA3
|
||||
0x37, // 0x14, VGA4 // 0x29, VGA4 ADJUSTED CS to 23!
|
||||
0x40, // 0x15, LOCK is Carrier SENSE
|
||||
0x76, // 0x16, FRONTEND
|
||||
0x87, // 0x17, ANALOG, RX=86/TX=87
|
||||
0x10, // 0x18, BUFF_SWING
|
||||
0x25, // 0x19, BUFF_CURRENT
|
||||
0xAE, // 0x1A, PLL_BW
|
||||
0x34, // 0x1B, CALIBRATE
|
||||
PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
|
||||
0xF0, // 0x1D, MATCH
|
||||
0x00, // 0x1E, PHASE_COMP
|
||||
0x00, // 0x1F, GAIN_COMP
|
||||
0x00, // 0x20, POWERDOWN
|
||||
0x4d, // 0x4d, // 0x21,
|
||||
0x10, // 0x10, // 0x22,
|
||||
0x06, // 0x06, // 0x23,
|
||||
0x00, // 0x00, // 0x24,
|
||||
0x40, // 0x40, // 0x25,
|
||||
0x00, // 0x00, // 0x26,
|
||||
0x00, // 0x00, // 0x27,
|
||||
// Not in real config of chipCon from here!!!
|
||||
ACK_TIMEOUT_19
|
||||
};
|
||||
|
||||
const uint8_t cc1020_config_115200[41] = {
|
||||
0x01, // 0x00, MAIN
|
||||
0x0F, // 0x01, INTERFACE
|
||||
0xFF, // 0x02, RESET
|
||||
0x8F, // 0x03, SEQUENCING
|
||||
// 869.525 at 200kHz
|
||||
0x3A, // 0x04, FREQ_2A
|
||||
0x32, // 0x05, FREQ_1A
|
||||
0x97, // 0x06, FREQ_0A // 19200
|
||||
0x29, // 0x07, CLOCK_A // 19200
|
||||
0x3A, // 0x08, FREQ_2B
|
||||
0x37, // 0x09, FREQ_1B
|
||||
0xEB, // 0x0A, FREQ_0B // 19200
|
||||
0x29, // 0x0B, CLOCK_B // 19200
|
||||
0x44, // 0x0C, VCO 44
|
||||
0x51, // 0x0D, MODEM Manchester
|
||||
0x58, // 0x0E, DEVIATION // FSK
|
||||
0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
|
||||
0x80, // 0x10, FILTER Bandwith 307.2kHz, i.e. channel spacing 500 kHz
|
||||
0x61, // 0x11, VGA1
|
||||
0x57, // 0x12, VGA2
|
||||
0x30, // 0x13, VGA3
|
||||
0x35, // 0x14, VGA4
|
||||
0x20, // 0x15, LOCK is Carrier SENSE
|
||||
0x76, // 0x16, FRONTEND
|
||||
0x87, // 0x17, ANALOG, RX=86/TX=87
|
||||
0x10, // 0x18, BUFF_SWING
|
||||
0x25, // 0x19, BUFF_CURRENT
|
||||
0xAE, // 0x1A, PLL_BW
|
||||
0x34, // 0x1B, CALIBRATE
|
||||
PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
|
||||
0xF0, // 0x1D, MATCH
|
||||
0x00, // 0x1E, PHASE_COMP
|
||||
0x00, // 0x1F, GAIN_COMP
|
||||
0x00, // 0x20, POWERDOWN
|
||||
0x4d, // 0x21,
|
||||
0x10, // 0x22,
|
||||
0x06, // 0x23,
|
||||
0x00, // 0x24,
|
||||
0x40, // 0x25,
|
||||
0x00, // 0x26,
|
||||
0x00, // 0x27,
|
||||
// Not in real config of chipCon from here!!!
|
||||
ACK_TIMEOUT_115
|
||||
};
|
||||
|
||||
/// cc1020 state
|
||||
enum cc1020_state {
|
||||
CC1020_OFF = 0,
|
||||
CC1020_RX = 0x01,
|
||||
CC1020_TX = 0x02,
|
||||
|
||||
CC1020_RX_SEARCHING = 0x10, // searching for preamble + sync word
|
||||
CC1020_RX_RECEIVING = 0x20, // receiving bytes
|
||||
CC1020_RX_PROCESSING = 0x40, // processing data in buffer
|
||||
|
||||
CC1020_OP_STATE = 0x73,
|
||||
|
||||
CC1020_TURN_OFF = 0x80,
|
||||
};
|
||||
|
||||
#define CC1020_SET_OPSTATE(opstate) cc1020_state = ((cc1020_state & ~CC1020_OP_STATE) | (opstate))
|
||||
|
||||
/******************************************************************************
|
||||
* @name Packet specification
|
||||
* @{
|
||||
*/
|
||||
|
||||
// header: number of bytes in packet including header
|
||||
struct cc1020_header {
|
||||
uint8_t pad;
|
||||
uint8_t length;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
#define CC1020_BUFFERSIZE 128
|
||||
|
||||
|
||||
#define PREAMBLE_SIZE 6
|
||||
#define PREAMBLE 0xAA
|
||||
|
||||
#define SYNCWORD_SIZE 2
|
||||
#define HDR_SIZE (sizeof (struct cc1020_header))
|
||||
|
||||
#define CRC_SIZE 2
|
||||
|
||||
#define TAIL_SIZE 2
|
||||
#define TAIL 0xFA
|
||||
|
||||
|
||||
///@}
|
||||
|
||||
#endif /* CC1020_INTERNAL_H */
|
||||
|
|
|
|||
|
|
@ -1,77 +1,77 @@
|
|||
/*
|
||||
Copyright 2006, Freie Universitaet Berlin. All rights reserved.
|
||||
|
||||
These sources were developed at the Freie Universitaet Berlin, Computer
|
||||
Systems and Telematics group.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
- Neither the name of Freie Universitaet Berlin (FUB) nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
This software is provided by FUB and the contributors on an "as is"
|
||||
basis, without any representations or warranties of any kind, express
|
||||
or implied including, but not limited to, representations or
|
||||
warranties of non-infringement, merchantability or fitness for a
|
||||
particular purpose. In no event shall FUB or contributors be liable
|
||||
for any direct, indirect, incidental, special, exemplary, or
|
||||
consequential damages (including, but not limited to, procurement of
|
||||
substitute goods or services; loss of use, data, or profits; or
|
||||
business interruption) however caused and on any theory of liability,
|
||||
whether in contract, strict liability, or tort (including negligence
|
||||
or otherwise) arising in any way out of the use of this software, even
|
||||
if advised of the possibility of such damage.
|
||||
|
||||
This implementation was developed by the CST group at the FUB.
|
||||
|
||||
For documentation and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de and the mailinglist
|
||||
scatterweb@lists.spline.inf.fu-berlin.de (subscription via the Website).
|
||||
Berlin, 2006
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file cc1020.h
|
||||
* \author FUB ScatterWeb Developers, Michael Baar, Nicolas Tsiftes
|
||||
**/
|
||||
|
||||
#ifndef CC1020_H
|
||||
#define CC1020_H
|
||||
|
||||
#include "dev/radio.h"
|
||||
|
||||
extern const uint8_t cc1020_config_19200[];
|
||||
extern const uint8_t cc1020_config_115200[];
|
||||
|
||||
#if 0
|
||||
void cc1020_init(const uint8_t* config);
|
||||
#endif
|
||||
void cc1020_set_rx(void);
|
||||
void cc1020_set_tx(void);
|
||||
void cc1020_set_power(uint8_t pa_power);
|
||||
int cc1020_carrier_sense(void);
|
||||
uint8_t cc1020_get_rssi(void);
|
||||
uint8_t cc1020_get_packet_rssi(void);
|
||||
int cc1020_sending(void);
|
||||
#if 0
|
||||
int cc1020_send(const void *buf, unsigned short size);
|
||||
int cc1020_read(void *buf, unsigned short size);
|
||||
void cc1020_set_receiver(void (*recv)(const struct radio_driver *));
|
||||
int cc1020_on(void);
|
||||
int cc1020_off(void);
|
||||
#endif
|
||||
extern const struct radio_driver cc1020_driver;
|
||||
|
||||
PROCESS_NAME(cc1020_sender_process);
|
||||
|
||||
#endif
|
||||
/*
|
||||
Copyright 2006, Freie Universitaet Berlin. All rights reserved.
|
||||
|
||||
These sources were developed at the Freie Universitaet Berlin, Computer
|
||||
Systems and Telematics group.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:
|
||||
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
|
||||
- Neither the name of Freie Universitaet Berlin (FUB) nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
This software is provided by FUB and the contributors on an "as is"
|
||||
basis, without any representations or warranties of any kind, express
|
||||
or implied including, but not limited to, representations or
|
||||
warranties of non-infringement, merchantability or fitness for a
|
||||
particular purpose. In no event shall FUB or contributors be liable
|
||||
for any direct, indirect, incidental, special, exemplary, or
|
||||
consequential damages (including, but not limited to, procurement of
|
||||
substitute goods or services; loss of use, data, or profits; or
|
||||
business interruption) however caused and on any theory of liability,
|
||||
whether in contract, strict liability, or tort (including negligence
|
||||
or otherwise) arising in any way out of the use of this software, even
|
||||
if advised of the possibility of such damage.
|
||||
|
||||
This implementation was developed by the CST group at the FUB.
|
||||
|
||||
For documentation and questions please use the web site
|
||||
http://scatterweb.mi.fu-berlin.de and the mailinglist
|
||||
scatterweb@lists.spline.inf.fu-berlin.de (subscription via the Website).
|
||||
Berlin, 2006
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file cc1020.h
|
||||
* \author FUB ScatterWeb Developers, Michael Baar, Nicolas Tsiftes
|
||||
**/
|
||||
|
||||
#ifndef CC1020_H
|
||||
#define CC1020_H
|
||||
|
||||
#include "dev/radio.h"
|
||||
|
||||
extern const uint8_t cc1020_config_19200[];
|
||||
extern const uint8_t cc1020_config_115200[];
|
||||
|
||||
#if 0
|
||||
void cc1020_init(const uint8_t* config);
|
||||
#endif
|
||||
void cc1020_set_rx(void);
|
||||
void cc1020_set_tx(void);
|
||||
void cc1020_set_power(uint8_t pa_power);
|
||||
int cc1020_carrier_sense(void);
|
||||
uint8_t cc1020_get_rssi(void);
|
||||
uint8_t cc1020_get_packet_rssi(void);
|
||||
int cc1020_sending(void);
|
||||
#if 0
|
||||
int cc1020_send(const void *buf, unsigned short size);
|
||||
int cc1020_read(void *buf, unsigned short size);
|
||||
void cc1020_set_receiver(void (*recv)(const struct radio_driver *));
|
||||
int cc1020_on(void);
|
||||
int cc1020_off(void);
|
||||
#endif
|
||||
extern const struct radio_driver cc1020_driver;
|
||||
|
||||
PROCESS_NAME(cc1020_sender_process);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue