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x86: Add support for (paging-based) protection domains

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This patch implements a simple, lightweight form of protection domains
using a pluggable framework.  Currently, the following plugin is
available:

 - Flat memory model with paging.

The overall goal of a protection domain implementation within this
framework is to define a set of resources that should be accessible to
each protection domain and to prevent that protection domain from
accessing other resources.  The details of each implementation of
protection domains may differ substantially, but they should all be
guided by the principle of least privilege.  However, that idealized
principle is balanced against the practical objectives of limiting the
number of relatively time-consuming context switches and minimizing
changes to existing code.

For additional information, please refer to cpu/x86/mm/README.md.

This patch also causes the C compiler to be used as the default linker
and assembler.
This commit is contained in:
Michael LeMay 2015-08-10 08:34:02 -07:00
parent b0de416682
commit 3908253038
48 changed files with 3558 additions and 295 deletions
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46
cpu/x86/drivers/quarkX1000/gpio.c
View file

@ -30,8 +30,11 @@
#include "gpio.h"
#include <stdbool.h>
#include "helpers.h"
#include "paging.h"
#include "shared-isr.h"
#include "syscalls.h"
/* GPIO Controler Registers */
#define SWPORTA_DR 0x00
@ -51,25 +54,55 @@
#define GPIO_IRQ 9
#define HIGHEST_REG LS_SYNC
#define MMIO_SZ MIN_PAGE_SIZE
PROT_DOMAINS_ALLOC(pci_driver_t, drv);
struct gpio_internal_data {
pci_driver_t pci;
quarkX1000_gpio_callback callback;
};
static struct gpio_internal_data data;
void quarkX1000_gpio_mmin(uint32_t offset, uint32_t *res);
SYSCALLS_DEFINE_SINGLETON(quarkX1000_gpio_mmin, drv,
uint32_t offset, uint32_t *res)
{
uint32_t *loc_res;
PROT_DOMAINS_VALIDATE_PTR(loc_res, res, sizeof(*res));
if(HIGHEST_REG < offset) {
halt();
}
PCI_MMIO_READL(drv, *loc_res, offset);
}
static inline uint32_t
read(uint32_t offset)
{
uint32_t res;
PCI_MMIO_READL(data.pci, res, offset);
quarkX1000_gpio_mmin(offset, &res);
return res;
}
void quarkX1000_gpio_mmout(uint32_t offset, uint32_t val);
SYSCALLS_DEFINE_SINGLETON(quarkX1000_gpio_mmout, drv,
uint32_t offset, uint32_t val)
{
if(HIGHEST_REG < offset) {
halt();
}
PCI_MMIO_WRITEL(drv, offset, val);
}
static inline void
write(uint32_t offset, uint32_t val)
{
PCI_MMIO_WRITEL(data.pci, offset, val);
quarkX1000_gpio_mmout(offset, val);
}
/* value must be 0x0 or 0x1 */
@ -231,7 +264,12 @@ quarkX1000_gpio_init(void)
pci_command_enable(pci_addr, PCI_CMD_1_MEM_SPACE_EN);
pci_init(&data.pci, pci_addr, 0);
PROT_DOMAINS_INIT_ID(drv);
pci_init(&drv, pci_addr, MMIO_SZ, 0, 0);
SYSCALLS_INIT(quarkX1000_gpio_mmin);
SYSCALLS_AUTHZ(quarkX1000_gpio_mmin, drv);
SYSCALLS_INIT(quarkX1000_gpio_mmout);
SYSCALLS_AUTHZ(quarkX1000_gpio_mmout, drv);
data.callback = 0;