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2eb3c2a492
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@ -114,7 +114,7 @@ uart0_init(unsigned long ubr)
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UCA0CTL1 |= UCSWRST; /* Hold peripheral in reset state */
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UCA0CTL1 |= UCSWRST; /* Hold peripheral in reset state */
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UCA0CTL1 |= UCSSEL_2; /* CLK = SMCLK */
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UCA0CTL1 |= UCSSEL_2; /* CLK = SMCLK */
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UCA0BR0 = 0x45; /* 8MHz/115200 = 69 = 0x45 */
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UCA0BR0 = ubr; /* 8MHz/115200 = 69 = 0x45 */
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UCA0BR1 = 0x00;
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UCA0BR1 = 0x00;
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UCA0MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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UCA0MCTL = UCBRS_3; /* Modulation UCBRSx = 3 */
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