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Merge pull request #691 from hexluthor/rts-cts

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CC2538: Add hardware flow control (RTS/CTS) support on UART1.
This commit is contained in:
George Oikonomou 2014-06-04 09:22:58 +01:00
parent ba9c2d40eb 274b3dcd0b
commit 2e166a83c7
2 changed files with 20 additions and 4 deletions
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22
cpu/cc2538/dev/uart.c
View file

@ -287,10 +287,6 @@ uart_init(uint8_t uart)
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port), GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rx.port),
GPIO_PIN_MASK(regs->rx.pin)); GPIO_PIN_MASK(regs->rx.pin));
if(regs->cts.port >= 0 || regs->rts.port >= 0) {
/* TODO Hardware flow control */
}
/* /*
* UART Interrupt Masks: * UART Interrupt Masks:
* Acknowledge RX and RX Timeout * Acknowledge RX and RX Timeout
@ -312,6 +308,24 @@ uart_init(uint8_t uart)
/* UART Control: 8N1 with FIFOs */ /* UART Control: 8N1 with FIFOs */
REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN; REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/*
* Enable hardware flow control (RTS/CTS) if requested.
* Note that hardware flow control is available only on UART1.
*/
if(regs->cts.port >= 0) {
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
}
if(regs->rts.port >= 0) {
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
}
/* UART Enable */ /* UART Enable */
REG(regs->base | UART_CTL) |= UART_CTL_UARTEN; REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;

2
cpu/cc2538/dev/uart.h
View file

@ -165,6 +165,8 @@
/** \name UART_CTL Register Bit-Masks /** \name UART_CTL Register Bit-Masks
* @{ * @{
*/ */
#define UART_CTL_CTSEN 0x00008000 /**< UART CTS flow-control enable (UART1 only) */
#define UART_CTL_RTSEN 0x00004000 /**< UART RTS flow-control enable (UART1 only) */
#define UART_CTL_RXE 0x00000200 /**< UART receive enable */ #define UART_CTL_RXE 0x00000200 /**< UART receive enable */
#define UART_CTL_TXE 0x00000100 /**< UART transmit enable */ #define UART_CTL_TXE 0x00000100 /**< UART transmit enable */
#define UART_CTL_LBE 0x00000080 /**< UART loop back enable */ #define UART_CTL_LBE 0x00000080 /**< UART loop back enable */