enabled softclk timeouts
fixed post interleaving problem fixed interrupts in ResumeMACASync. This seems quite solid now.
This commit is contained in:
Mariano Alvira
parent
d3f6ef07f2
commit
2a07cbe665
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@ -434,6 +434,8 @@ enum maca_status_bits {
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#define filter_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_flt)
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#define checksum_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_crc)
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#define data_indication_irq() bit_is_set(*MACA_IRQ,maca_irq_di)
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#define softclock_irq() bit_is_set(*MACA_IRQ,maca_irq_sftclk)
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#define poll_irq() bit_is_set(*MACA_IRQ,maca_irq_poll)
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#define status_is_not_completed() ((*MACA_STATUS & 0xffff) == maca_cc_not_completed)
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#define status_is_success() ((*MACA_STATUS & 0xffff) == maca_cc_success)
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74
lib/maca.c
74
lib/maca.c
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@ -21,7 +21,7 @@
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#define CLK_PER_BYTE 8
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#ifndef RECV_SOFTIMEOUT
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#define RECV_SOFTIMEOUT (8*128*CLK_PER_BYTE) /* 4 128 byte packets */
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#define RECV_SOFTIMEOUT (8*128*CLK_PER_BYTE)
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#endif
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#define MAX_PACKET_SIZE (MAX_PAYLOAD_SIZE + 2) /* packet includes 2 bytes of checksum */
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@ -140,7 +140,9 @@ void post_receive(void) {
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(1 << maca_ctrl_asap) | ( 4 << PRECOUNT) |
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(1 << maca_ctrl_prm) |
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(maca_ctrl_seq_rx));*/
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for(i=0; i<1000; i++) { continue; }
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/* status bit 10 is set immediately */
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/* then 11, 10, and 9 get set */
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/* they are cleared once we get back to maca_isr */
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}
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@ -156,7 +158,6 @@ volatile packet_t* rx_packet(void) {
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// print_packets("rx_packet");
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irq_restore();
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if(get_field(*MACA_STATUS,CODE) != NOT_COMPLETED) { post_receive(); }
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return p;
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}
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@ -177,15 +178,13 @@ void post_tx(void) {
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*MACA_DMARX = (uint32_t)&(dma_rx->data[0]);
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/* disable soft timeout clock */
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/* disable start clock */
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*MACA_TMRDIS = (1 << maca_tmren_sft) | ( 1 << maca_tmren_strt ) ;
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*MACA_TMRDIS = (1 << maca_tmren_sft) | ( 1<< maca_tmren_cpl) | ( 1 << maca_tmren_strt ) ;
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/* this doesn't work right */
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/* lock up seems to happen when switching from receive to transmitt */
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/* set complete clock to long value */
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/* acts like a watchdog incase the MACA locks up */
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// *MACA_CPLCLK = *MACA_CLK + (CLK_PER_BYTE * dma_tx->length+6) + (CLK_PER_BYTE * 0);
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/* acts like a watchdog in case the MACA locks up */
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*MACA_CPLCLK = *MACA_CLK + (CLK_PER_BYTE * 256);
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/* enable complete clock */
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// *MACA_TMREN = (1 << maca_tmren_cpl);
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*MACA_TMREN = (1 << maca_tmren_cpl);
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enable_irq(MACA);
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*MACA_CONTROL = ( (1 << maca_ctrl_prm) | ( 4 << PRECOUNT) |
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@ -196,6 +195,9 @@ void post_tx(void) {
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(maca_ctrl_mode_no_cca << maca_ctrl_mode) |
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(1 << maca_ctrl_asap) |
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(maca_ctrl_seq_tx)); */
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/* status bit 10 is set immediately */
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/* then 11, 10, and 9 get set */
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/* they are cleared once we get back to maca_isr */
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}
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void tx_packet(volatile packet_t *p) {
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@ -216,7 +218,6 @@ void tx_packet(volatile packet_t *p) {
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}
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// print_packets("tx packet");
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irq_restore();
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if(get_field(*MACA_STATUS,CODE) != NOT_COMPLETED) { post_tx(); }
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return;
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}
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@ -344,6 +345,15 @@ void maca_isr(void) {
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// print_packets("maca_isr");
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if (bit_is_set(*MACA_STATUS, maca_status_ovr))
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PRINTF("maca overrun\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_busy))
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PRINTF("maca busy\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_crc))
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PRINTF("maca crc error\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_to))
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PRINTF("maca timeout\n\r");
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if (data_indication_irq()) {
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*MACA_CLRIRQ = (1 << maca_irq_di);
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dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
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@ -361,6 +371,12 @@ void maca_isr(void) {
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ResumeMACASync();
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*MACA_CLRIRQ = (1 << maca_irq_crc);
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}
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if (softclock_irq()) {
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*MACA_CLRIRQ = (1 << maca_irq_sftclk);
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}
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if (poll_irq()) {
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*MACA_CLRIRQ = (1 << maca_irq_poll);
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}
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if(action_complete_irq()) {
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/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
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if(last_post == TX_POST) {
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@ -370,26 +386,17 @@ void maca_isr(void) {
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ResumeMACASync();
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*MACA_CLRIRQ = (1 << maca_irq_acpl);
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}
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i = *MACA_IRQ;
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if (i != 0)
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PRINTF("*MACA_IRQ %x\n\r", i);
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if (bit_is_set(*MACA_STATUS, maca_status_ovr))
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PRINTF("maca overrun\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_busy))
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PRINTF("maca busy\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_crc))
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PRINTF("maca crc error\n\r");
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if (bit_is_set(*MACA_STATUS, maca_status_to))
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PRINTF("maca timeout\n\r");
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decode_status();
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if (*MACA_IRQ != 0)
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PRINTF("*MACA_IRQ %x\n\r", *MACA_IRQ);
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if(tx_head != 0) {
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post_tx();
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} else if(last_post != TX_POST) {
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} else {
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post_receive();
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}
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}
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}
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@ -410,7 +417,7 @@ void init_phy(void)
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for(cnt = 0; cnt < 400000; cnt++) {};
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*MACA_TMREN = (1 << maca_tmren_strt) | (1 << maca_tmren_cpl);
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// *MACA_TMREN = (1 << maca_tmren_strt) | (1 << maca_tmren_cpl);
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*MACA_CLKDIV = MACA_CLOCK_DIV;
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*MACA_WARMUP = 0x00180012;
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*MACA_EOFDELAY = 0x00000004;
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@ -418,8 +425,14 @@ void init_phy(void)
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*MACA_TXCCADELAY = 0x00000025;
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*MACA_FRAMESYNC0 = 0x000000A7;
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*MACA_CLK = 0x00000008;
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*MACA_MASKIRQ = ((1 << maca_irq_rst) | (1 << maca_irq_acpl) | (1 << maca_irq_cm) |
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(1 << maca_irq_flt) | (1 << maca_irq_crc) | (1 << maca_irq_di));
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*MACA_MASKIRQ = ((1 << maca_irq_rst) |
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(1 << maca_irq_acpl) |
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(1 << maca_irq_cm) |
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(1 << maca_irq_flt) |
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(1 << maca_irq_crc) |
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(1 << maca_irq_di) |
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(1 << maca_irq_sftclk)
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);
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*MACA_SLOTOFFSET = 0x00350000;
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}
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@ -885,10 +898,9 @@ void ResumeMACASync(void)
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{
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volatile uint32_t clk, TsmRxSteps, LastWarmupStep, LastWarmupData, LastWarmdownStep, LastWarmdownData;
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// bool_t tmpIsrStatus;
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volatile uint32_t i, saved_irq;
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volatile uint32_t i, macairq;
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safe_irq_disable(MACA);
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// disable_irq(MACA);
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// saved_irq = *MACA_IRQ;
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// ITC_DisableInterrupt(gMacaInt_c);
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// AppInterrupts_ProtectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
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@ -936,7 +948,7 @@ void ResumeMACASync(void)
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// AppInterrupts_UnprotectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
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// ITC_EnableInterrupt(gMacaInt_c);
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// *MACA_IRQ = saved_irq;
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// enable_irq(MACA);
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irq_restore();
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}
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@ -47,7 +47,7 @@ uint32_t get_time(void) {
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#define random_short_addr() (*MACA_RANDOM & ones(sizeof(short_addr_t)*8))
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void build_session_req(volatile packet_t *p) {
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p->length = 4; p->offset = 0;
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p->length = 125; p->offset = 0;
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p->data[0] = 0x01;
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p->data[1] = 0x02;
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p->data[2] = 0x03;
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@ -96,7 +96,10 @@ void main(void) {
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set_power(0x0f); /* 0dbm */
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set_channel(0); /* channel 11 */
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/* enable MACA interrupts */
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/* call the handler once to start the maca cycle */
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enable_irq(MACA);
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maca_isr();
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/* initial radio command */
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/* nop, promiscuous, no cca */
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