diff --git a/cpu/x86/Makefile.x86_quarkX1000 b/cpu/x86/Makefile.x86_quarkX1000
index ec9da64be..e5c0b1801 100644
--- a/cpu/x86/Makefile.x86_quarkX1000
+++ b/cpu/x86/Makefile.x86_quarkX1000
@@ -3,6 +3,7 @@ include $(CONTIKI)/cpu/x86/Makefile.x86_common
 CONTIKI_CPU_DIRS += drivers/legacy_pc drivers/quarkX1000 init/legacy_pc
 
 CONTIKI_SOURCEFILES += bootstrap_quarkX1000.S rtc.c pit.c pic.c irq.c nmi.c pci.c uart-16x50.c uart.c gpio.c i2c.c eth.c shared-isr.c
+CONTIKI_SOURCEFILES += msg-bus.c
 
 CFLAGS += -m32 -march=i586 -mtune=i586
 LDFLAGS += -m32 -Xlinker -T -Xlinker $(CONTIKI)/cpu/x86/quarkX1000.ld
diff --git a/cpu/x86/drivers/quarkX1000/msg-bus.c b/cpu/x86/drivers/quarkX1000/msg-bus.c
new file mode 100644
index 000000000..e7a4bca44
--- /dev/null
+++ b/cpu/x86/drivers/quarkX1000/msg-bus.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "msg-bus.h"
+#include "pci.h"
+
+/** Message bus control register */
+#define MCR_PCI_REG_ADDR 0xD0
+/** Message data register */
+#define MDR_PCI_REG_ADDR 0xD4
+/** Message control register extension */
+#define MCRX_PCI_REG_ADDR 0xD8
+
+typedef union mcr {
+  struct {
+    uint32_t         : 4;
+    uint32_t byte_en : 4;
+    uint32_t reg_off : 8;
+    uint32_t port    : 8;
+    uint32_t opcode  : 8;
+  };
+  uint32_t raw;
+} mcr_t;
+
+typedef union mcrx {
+  struct {
+    uint32_t           : 8;
+    uint32_t reg_off   : 24;
+  };
+  uint32_t raw;
+} mcrx_t;
+
+/*---------------------------------------------------------------------------*/
+static void
+request_op(uint8_t port, uint32_t reg_off, uint8_t opcode)
+{
+  pci_config_addr_t pci_addr = { .raw = 0 };
+  mcr_t mcr = { .raw = 0 };
+  mcrx_t mcrx = { .raw = 0 };
+
+  pci_addr.reg_off = MCR_PCI_REG_ADDR;
+  mcr.opcode = opcode;
+  mcr.byte_en = 0xF;
+  mcr.port = port;
+  mcr.reg_off = reg_off & 0xFF;
+  pci_config_write(pci_addr, mcr.raw);
+
+  pci_addr.reg_off = MCRX_PCI_REG_ADDR;
+  mcrx.reg_off = reg_off >> 8;
+  pci_config_write(pci_addr, mcrx.raw);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief         Read from a message bus register.
+ * \param port    Port of message bus register to be read.
+ * \param reg_off Register/offset identifier of message bus register to read.
+ * \param val     Storage location for value that has been read.
+ */
+void
+quarkX1000_msg_bus_read(uint8_t port, uint32_t reg_off, uint32_t *val)
+{
+  pci_config_addr_t pci_addr = { .raw = 0 };
+
+  request_op(port, reg_off, 0x10);
+
+  pci_addr.reg_off = MDR_PCI_REG_ADDR;
+  *val = pci_config_read(pci_addr);
+}
+/*---------------------------------------------------------------------------*/
+/**
+ * \brief         Write to a message bus register.
+ * \param port    Port of message bus register to be written.
+ * \param reg_off Register/offset identifier of message bus register to write.
+ * \param val     Value to write.
+ */
+void
+quarkX1000_msg_bus_write(uint8_t port, uint32_t reg_off, uint32_t val)
+{
+  pci_config_addr_t pci_addr = { .raw = 0 };
+
+  pci_addr.reg_off = MDR_PCI_REG_ADDR;
+  pci_config_write(pci_addr, val);
+
+  request_op(port, reg_off, 0x11);
+}
+/*---------------------------------------------------------------------------*/
diff --git a/cpu/x86/drivers/quarkX1000/msg-bus.h b/cpu/x86/drivers/quarkX1000/msg-bus.h
new file mode 100644
index 000000000..0b810e06d
--- /dev/null
+++ b/cpu/x86/drivers/quarkX1000/msg-bus.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU_X86_DRIVERS_QUARKX1000_MSG_BUS_H_
+#define CPU_X86_DRIVERS_QUARKX1000_MSG_BUS_H_
+
+#include <stdint.h>
+
+/* Routines for accessing the message bus.
+ *
+ * The Intel Quark X1000 SoC includes a message bus that is accessible
+ * via PCI configuration registers.  It communicates to various SoC
+ * components such as the Isolated Memory Region (IMR) registers and the
+ * Remote Management Unit.
+ *
+ * Refer to Intel Quark SoC X1000 Datasheet, Section 12.5 for more details on
+ * the message bus.
+ */
+
+void quarkX1000_msg_bus_read(uint8_t port, uint32_t reg_off, uint32_t *val);
+void quarkX1000_msg_bus_write(uint8_t port, uint32_t reg_off, uint32_t val);
+
+#endif /* CPU_X86_DRIVERS_QUARKX1000_MSG_BUS_H_ */
diff --git a/platform/galileo/README.md b/platform/galileo/README.md
index 815b09011..63c929c4f 100644
--- a/platform/galileo/README.md
+++ b/platform/galileo/README.md
@@ -33,6 +33,7 @@ Device drivers:
   * I2C
   * GPIO (default pinmux configuration is listed in
     platform/galileo/drivers/galileo-pinmux.c)
+  * Intel Quark X1000 SoC message bus
 
 Contiki APIs:
   * Clock module