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fix these for the putchr and putstr name changes

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This commit is contained in:
Mariano Alvira 2010-03-02 10:39:47 -05:00
parent 52bd134d4a
commit 225fb3e553
5 changed files with 69 additions and 69 deletions
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46
tests/flasher.c
View file

@ -6,14 +6,14 @@
#define DEBUG 1 #define DEBUG 1
#if DEBUG #if DEBUG
#define dbg_putc(...) putc(__VA_ARGS__) #define dbg_putchr(...) putchr(__VA_ARGS__)
#define dbg_puts(...) puts(__VA_ARGS__) #define dbg_putstr(...) putstr(__VA_ARGS__)
#define dbg_put_hex(...) put_hex(__VA_ARGS__) #define dbg_put_hex(...) put_hex(__VA_ARGS__)
#define dbg_put_hex16(...) put_hex16(__VA_ARGS__) #define dbg_put_hex16(...) put_hex16(__VA_ARGS__)
#define dbg_put_hex32(...) put_hex32(__VA_ARGS__) #define dbg_put_hex32(...) put_hex32(__VA_ARGS__)
#else #else
#define dbg_putc(...) #define dbg_putchr(...)
#define dbg_puts(...) #define dbg_putstr(...)
#define dbg_put_hex(...) #define dbg_put_hex(...)
#define dbg_put_hex16(...) #define dbg_put_hex16(...)
#define dbg_put_hex32(...) #define dbg_put_hex32(...)
@ -45,30 +45,30 @@ void main(void) {
vreg_init(); vreg_init();
dbg_puts("Detecting internal nvm\n\r"); dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type); err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_puts("nvm_detect returned: 0x"); dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err); dbg_put_hex(err);
dbg_puts(" type is: 0x"); dbg_putstr(" type is: 0x");
dbg_put_hex32(type); dbg_put_hex32(type);
dbg_puts("\n\r"); dbg_putstr("\n\r");
/* erase the flash */ /* erase the flash */
err = nvm_erase(gNvmInternalInterface_c, type, 0x4fffffff); err = nvm_erase(gNvmInternalInterface_c, type, 0x4fffffff);
dbg_puts("nvm_erase returned: 0x"); dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err); dbg_put_hex(err);
dbg_puts("\n\r"); dbg_putstr("\n\r");
dbg_puts(" type is: 0x"); dbg_putstr(" type is: 0x");
dbg_put_hex32(type); dbg_put_hex32(type);
dbg_puts("\n\r"); dbg_putstr("\n\r");
/* say we are ready */ /* say we are ready */
len = 0; len = 0;
puts("ready"); putstr("ready");
flushrx(); flushrx();
/* read the length */ /* read the length */
@ -78,9 +78,9 @@ void main(void) {
len += (c<<(i*8)); len += (c<<(i*8));
} }
dbg_puts("len: "); dbg_putstr("len: ");
dbg_put_hex32(len); dbg_put_hex32(len);
dbg_puts("\n\r"); dbg_putstr("\n\r");
/* write the OKOK magic */ /* write the OKOK magic */
@ -92,15 +92,15 @@ void main(void) {
((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O'; ((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O';
#endif #endif
dbg_puts(" type is: 0x"); dbg_putstr(" type is: 0x");
dbg_put_hex32(type); dbg_put_hex32(type);
dbg_puts("\n\r"); dbg_putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4); err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4);
dbg_puts("nvm_write returned: 0x"); dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err); dbg_put_hex(err);
dbg_puts("\n\r"); dbg_putstr("\n\r");
/* write the length */ /* write the length */
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&len, 4, 4); err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&len, 4, 4);
@ -113,7 +113,7 @@ void main(void) {
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 8+i, 1); err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 8+i, 1);
} }
puts("flasher done\n\r"); putstr("flasher done\n\r");
state = SCAN_X; addr=0; state = SCAN_X; addr=0;
while((c=getc())) { while((c=getc())) {
@ -139,11 +139,11 @@ void main(void) {
} else { } else {
/* string is data to write */ /* string is data to write */
data = to_u32(buf); data = to_u32(buf);
puts("writing addr "); putstr("writing addr ");
put_hex32(addr); put_hex32(addr);
puts(" data "); putstr(" data ");
put_hex32(data); put_hex32(data);
puts("\n\r"); putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4); err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4);
addr += 4; addr += 4;
} }

16
tests/nvm-read.c
View file

@ -16,27 +16,27 @@ void main(void) {
vreg_init(); vreg_init();
puts("Detecting internal nvm\n\r"); putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type); err = nvm_detect(gNvmInternalInterface_c, &type);
puts("nvm_detect returned: 0x"); putstr("nvm_detect returned: 0x");
put_hex(err); put_hex(err);
puts(" type is: 0x"); putstr(" type is: 0x");
put_hex32(type); put_hex32(type);
puts("\n\r"); putstr("\n\r");
nvm_setsvar(0); nvm_setsvar(0);
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, READ_ADDR, READ_NBYTES); err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, READ_ADDR, READ_NBYTES);
puts("nvm_read returned: 0x"); putstr("nvm_read returned: 0x");
put_hex(err); put_hex(err);
puts("\n\r"); putstr("\n\r");
for(i=0; i<READ_NBYTES/4; i++) { for(i=0; i<READ_NBYTES/4; i++) {
puts("0x"); putstr("0x");
put_hex32(buf[i]); put_hex32(buf[i]);
puts("\n\r"); putstr("\n\r");
} }

32
tests/nvm-write.c
View file

@ -16,46 +16,46 @@ void main(void) {
vreg_init(); vreg_init();
puts("Detecting internal nvm\n\r"); putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type); err = nvm_detect(gNvmInternalInterface_c, &type);
puts("nvm_detect returned: 0x"); putstr("nvm_detect returned: 0x");
put_hex(err); put_hex(err);
puts(" type is: 0x"); putstr(" type is: 0x");
put_hex32(type); put_hex32(type);
puts("\n\r"); putstr("\n\r");
buf[0] = WRITEVAL0; buf[0] = WRITEVAL0;
buf[1] = WRITEVAL1; buf[1] = WRITEVAL1;
err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000); /* erase sector 30 --- sector 31 is the 'secret zone' */ err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000); /* erase sector 30 --- sector 31 is the 'secret zone' */
puts("nvm_erase returned: 0x"); putstr("nvm_erase returned: 0x");
put_hex(err); put_hex(err);
puts("\n\r"); putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES); err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
puts("nvm_write returned: 0x"); putstr("nvm_write returned: 0x");
put_hex(err); put_hex(err);
puts("\n\r"); putstr("\n\r");
puts("writing\n\r"); putstr("writing\n\r");
for(i=0; i<WRITE_NBYTES/4; i++) { for(i=0; i<WRITE_NBYTES/4; i++) {
puts("0x"); putstr("0x");
put_hex32(buf[i]); put_hex32(buf[i]);
puts("\n\r"); putstr("\n\r");
buf[i] = 0x00000000; /* clear buf for the read */ buf[i] = 0x00000000; /* clear buf for the read */
} }
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES); err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
puts("nvm_read returned: 0x"); putstr("nvm_read returned: 0x");
put_hex(err); put_hex(err);
puts("\n\r"); putstr("\n\r");
puts("reading\n\r"); putstr("reading\n\r");
for(i=0; i<WRITE_NBYTES/4; i++) { for(i=0; i<WRITE_NBYTES/4; i++) {
puts("0x"); putstr("0x");
put_hex32(buf[i]); put_hex32(buf[i]);
puts("\n\r"); putstr("\n\r");
} }

2
tests/romimg.c
View file

@ -10,7 +10,7 @@ void main(void) {
uart_init(INC, MOD); uart_init(INC, MOD);
for(data = DUMP_BASE; data < ((uint8_t *)(DUMP_BASE+DUMP_LEN)); data++) { for(data = DUMP_BASE; data < ((uint8_t *)(DUMP_BASE+DUMP_LEN)); data++) {
putc(*data); putchr(*data);
} }
while(1); while(1);

42
tests/sleep.c
View file

@ -13,19 +13,19 @@ void main(void) {
*mem32(0x0040fffc) = 0xface00ff; *mem32(0x0040fffc) = 0xface00ff;
*mem32(0x00410000) = 0xabcd0123; *mem32(0x00410000) = 0xabcd0123;
puts("sleep test\n\r"); putstr("sleep test\n\r");
puts("0x00401ffc: "); putstr("0x00401ffc: ");
put_hex32(*mem32(0x00401ffc)); put_hex32(*mem32(0x00401ffc));
puts("\r\n"); putstr("\r\n");
puts("0x00407ffc: "); putstr("0x00407ffc: ");
put_hex32(*mem32(0x00407ffc)); put_hex32(*mem32(0x00407ffc));
puts("\r\n"); putstr("\r\n");
puts("0x0040fffc: "); putstr("0x0040fffc: ");
put_hex32(*mem32(0x0040fffc)); put_hex32(*mem32(0x0040fffc));
puts("\r\n"); putstr("\r\n");
puts("0x00410000: "); putstr("0x00410000: ");
put_hex32(*mem32(0x00410000)); put_hex32(*mem32(0x00410000));
puts("\r\n"); putstr("\r\n");
/* radio must be OFF before sleeping */ /* radio must be OFF before sleeping */
/* otherwise MCU will not wake up properly */ /* otherwise MCU will not wake up properly */
@ -34,7 +34,7 @@ void main(void) {
#if USE_32KHZ #if USE_32KHZ
/* turn on the 32kHz crystal */ /* turn on the 32kHz crystal */
puts("enabling 32kHz crystal\n\r"); putstr("enabling 32kHz crystal\n\r");
/* you have to hold it's hand with this on */ /* you have to hold it's hand with this on */
/* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */ /* once you start the 32xHz crystal it can only be stopped with a reset (hard or soft) */
/* first, disable the ring osc */ /* first, disable the ring osc */
@ -49,14 +49,14 @@ void main(void) {
{ {
static volatile uint32_t old; static volatile uint32_t old;
old = *CRM_RTC_COUNT; old = *CRM_RTC_COUNT;
puts("waiting for xtal\n\r"); putstr("waiting for xtal\n\r");
while(*CRM_RTC_COUNT == old) { while(*CRM_RTC_COUNT == old) {
continue; continue;
} }
/* RTC has started up */ /* RTC has started up */
set_bit(*CRM_SYS_CNTL,5); set_bit(*CRM_SYS_CNTL,5);
puts("32kHZ xtal started\n\r"); putstr("32kHZ xtal started\n\r");
} }
#endif #endif
@ -105,19 +105,19 @@ void main(void) {
/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */ /* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */
*CRM_STATUS = 1; *CRM_STATUS = 1;
puts("\n\r\n\r\n\r"); putstr("\n\r\n\r\n\r");
puts("0x00401ffc: "); putstr("0x00401ffc: ");
put_hex32(*mem32(0x00401ffc)); put_hex32(*mem32(0x00401ffc));
puts("\r\n"); putstr("\r\n");
puts("0x00407ffc: "); putstr("0x00407ffc: ");
put_hex32(*mem32(0x00407ffc)); put_hex32(*mem32(0x00407ffc));
puts("\r\n"); putstr("\r\n");
puts("0x0040fffc: "); putstr("0x0040fffc: ");
put_hex32(*mem32(0x0040fffc)); put_hex32(*mem32(0x0040fffc));
puts("\r\n"); putstr("\r\n");
puts("0x00410000: "); putstr("0x00410000: ");
put_hex32(*mem32(0x00410000)); put_hex32(*mem32(0x00410000));
puts("\r\n"); putstr("\r\n");
*GPIO_PAD_DIR0 = LED_RED; *GPIO_PAD_DIR0 = LED_RED;
#define DELAY 400000 #define DELAY 400000