Merge pull request #606 from atiselsts/master
Fix MCU clock calibration in msp430f2xxx based platforms (e.g. Zolertia Z1)
This commit is contained in:
Nicolas Tsiftes
commit
1b49b68c3b
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@ -83,68 +83,6 @@ msp430_init_dco(void)
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/* DCO Internal Resistor */
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Start CPU with full speed (? good or bad?) and go downwards */
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/*---------------------------------------------------------------------------*/
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void
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msp430_quick_synch_dco(void) {
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uint16_t last;
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uint16_t diff;
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uint16_t dco_reg = 0x0fff;
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uint8_t current_bit = 12;
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uint16_t i;
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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#define DELTA_2 ((MSP430_CPU_SPEED) / 32768)
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/* Select SMCLK clock, and capture on ACLK for TBCCR6 */
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TBCTL = TBSSEL1 | TBCLR;
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TBCCTL6 = CCIS0 + CM0 + CAP;
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/* start the timer */
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TBCTL |= MC1;
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BCSCTL1 = 0x8D | 7;
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DCOCTL = 0xff; /* MAX SPEED ?? */
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/* IDEA: do binary search - check MSB first, etc... */
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/* 1 set current bit to zero - if to slow, put back to 1 */
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while(current_bit--) {
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/* first set the current bit to zero and check - we know that it is
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set from start so ^ works (first bit = bit 11) */
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dco_reg = dco_reg ^ (1 << current_bit); /* clear bit 11..10..9.. */
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/* set dco registers */
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DCOCTL = dco_reg & 0xff;
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BCSCTL1 = (BCSCTL1 & 0xf8) | (dco_reg >> 8);
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/* some delay to make clock stable - could possibly be made using
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captures too ... */
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for(i=0; i < 1000; i++) {
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i = i | 1;
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}
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/* do capture... */
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while(!(TBCCTL6 & CCIFG));
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last = TBCCR6;
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TBCCTL6 &= ~CCIFG;
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/* wait for next Capture - and calculate difference */
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - last;
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/* /\* store what was run during the specific test *\/ */
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/* dcos[current_bit] = dco_reg; */
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/* vals[current_bit] = diff; */
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/* should we keep the bit cleared or not ? */
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if(diff < DELTA_2) { /* DCO is too slow - fewer ticks than desired */
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/* toggle bit again to get it back to one */
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dco_reg = dco_reg ^ (1 << current_bit);
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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static void
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init_ports(void)
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{
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@ -224,7 +162,10 @@ msp430_cpu_init(void)
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dint();
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watchdog_init();
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init_ports();
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msp430_quick_synch_dco();
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/* set DCO to a reasonable default value (8MHz) */
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msp430_init_dco();
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/* calibrate the DCO step-by-step */
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msp430_sync_dco();
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eint();
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#if defined(__MSP430__) && defined(__GNUC__)
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if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */
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@ -282,13 +223,10 @@ int __low_level_init(void)
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}
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#endif
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/*---------------------------------------------------------------------------*/
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#if DCOSYNCH_CONF_ENABLED
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/* this code will always start the TimerB if not already started */
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void
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msp430_sync_dco(void) {
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uint16_t last;
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uint16_t diff;
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/* uint32_t speed; */
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uint16_t oldcapture;
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int16_t diff;
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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#define DELTA_2 ((MSP430_CPU_SPEED) / 32768)
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@ -298,36 +236,35 @@ msp430_sync_dco(void) {
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/* start the timer */
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TBCTL |= MC1;
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/* wait for next Capture */
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TBCCTL6 &= ~CCIFG;
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while(!(TBCCTL6 & CCIFG));
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last = TBCCR6;
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while(1) {
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/* wait for the next capture */
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TBCCTL6 &= ~CCIFG;
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while(!(TBCCTL6 & CCIFG));
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oldcapture = TBCCR6;
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TBCCTL6 &= ~CCIFG;
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/* wait for next Capture - and calculate difference */
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - last;
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/* wait for the next capture - and calculate difference */
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TBCCTL6 &= ~CCIFG;
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while(!(TBCCTL6 & CCIFG));
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diff = TBCCR6 - oldcapture;
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/* Stop timer - conserves energy according to user guide */
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TBCTL = 0;
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/* speed = diff; */
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/* speed = speed * 32768; */
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/* printf("Last TAR diff:%d target: %ld ", diff, DELTA_2); */
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/* printf("CPU Speed: %lu DCOCTL: %d\n", speed, DCOCTL); */
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/* resynchronize the DCO speed if not at target */
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if(DELTA_2 < diff) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else if(DELTA_2 > diff) {
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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/* resynchronize the DCO speed if not at target */
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if(DELTA_2 == diff) {
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break; /* if equal, leave "while(1)" */
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} else if(DELTA_2 < diff) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO roll under? */
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BCSCTL1--;
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}
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} else { /* -> Select next lower RSEL */
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO roll over? */
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BCSCTL1++;
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}
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/* -> Select next higher RSEL */
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}
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}
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/* Stop the timer - conserves energy according to user guide */
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TBCTL = 0;
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}
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#endif /* DCOSYNCH_CONF_ENABLED */
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/*---------------------------------------------------------------------------*/
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