Use additive offsets
OR-ing an offset to a base address instead of adding it is dangerous
because it can only work if the base address is aligned enough for the
offset.
Moreover, if the base address or the offset has a value unknown at
compile time, then the assembly instructions dedicated to 'base +
offset' addressing on most CPUs can't be emitted by the compiler because
this would require the alignment of the base address against the offset
to be known in order to optimize 'base | offset' into 'base + offset'.
In that case, the compiler has to emit more instructions in order to
compute 'base | offset' on most CPUs, e.g. on ARM, which means larger
binary size and slower execution.
Hence, replace all occurrences of 'base | offset' with 'base + offset'.
This must become a coding rule.
Here are the results for the cc2538-demo example:
- Compilation of uart_init():
* before:
REG(regs->base | UART_CC) = 0;
200b78: f446 637c orr.w r3, r6, #4032 ; 0xfc0
200b7c: f043 0308 orr.w r3, r3, #8
200b80: 2200 movs r2, #0
200b82: 601a str r2, [r3, #0]
* now:
REG(regs->base + UART_CC) = 0;
200b7a: 2300 movs r3, #0
200b7c: f8c4 3fc8 str.w r3, [r4, #4040] ; 0xfc8
- Size of the .text section:
* before: 0x4c7c
* now: 0x4c28
* saved: 84 bytes
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Benoît Thébaudeau
parent
c76316adf2
commit
19fd7a3551
7 changed files with 65 additions and 65 deletions
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@ -206,22 +206,22 @@ reset(uint32_t uart_base)
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uint32_t lchr;
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/* Make sure the UART is disabled before trying to configure it */
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REG(uart_base | UART_CTL) = UART_CTL_VALUE;
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REG(uart_base + UART_CTL) = UART_CTL_VALUE;
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/* Clear error status */
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REG(uart_base | UART_ECR) = 0xFF;
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REG(uart_base + UART_ECR) = 0xFF;
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/* Store LCHR configuration */
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lchr = REG(uart_base | UART_LCRH);
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lchr = REG(uart_base + UART_LCRH);
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/* Flush FIFOs by clearing LCHR.FEN */
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REG(uart_base | UART_LCRH) = 0;
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REG(uart_base + UART_LCRH) = 0;
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/* Restore LCHR configuration */
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REG(uart_base | UART_LCRH) = lchr;
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REG(uart_base + UART_LCRH) = lchr;
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/* UART Enable */
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REG(uart_base | UART_CTL) |= UART_CTL_UARTEN;
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REG(uart_base + UART_CTL) |= UART_CTL_UARTEN;
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}
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/*---------------------------------------------------------------------------*/
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static bool
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@ -232,7 +232,7 @@ permit_pm1(void)
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for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
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/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
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if((REG(SYS_CTRL_RCGCUART) & regs->sys_ctrl_rcgcuart_uart) != 0 &&
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(REG(regs->base | UART_FR) & UART_FR_TXFE) == 0) {
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(REG(regs->base + UART_FR) & UART_FR_TXFE) == 0) {
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return false;
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}
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}
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@ -261,7 +261,7 @@ uart_init(uint8_t uart)
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REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
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/* Run on SYS_DIV */
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REG(regs->base | UART_CC) = 0;
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REG(regs->base + UART_CC) = 0;
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/*
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* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
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@ -292,21 +292,21 @@ uart_init(uint8_t uart)
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* Acknowledge RX and RX Timeout
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* Acknowledge Framing, Overrun and Break Errors
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*/
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REG(regs->base | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(regs->base | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
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REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
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REG(regs->base | UART_IFLS) =
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REG(regs->base + UART_IFLS) =
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UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
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/* Make sure the UART is disabled before trying to configure it */
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REG(regs->base | UART_CTL) = UART_CTL_VALUE;
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REG(regs->base + UART_CTL) = UART_CTL_VALUE;
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/* Baud Rate Generation */
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REG(regs->base | UART_IBRD) = regs->ibrd;
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REG(regs->base | UART_FBRD) = regs->fbrd;
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REG(regs->base + UART_IBRD) = regs->ibrd;
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REG(regs->base + UART_FBRD) = regs->fbrd;
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/* UART Control: 8N1 with FIFOs */
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REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
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/*
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* Enable hardware flow control (RTS/CTS) if requested.
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@ -316,18 +316,18 @@ uart_init(uint8_t uart)
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REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
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ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
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REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
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REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
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}
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if(regs->rts.port >= 0) {
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ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
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GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
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ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
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REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
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REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
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}
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/* UART Enable */
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REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
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REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
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/* Enable UART0 Interrupts */
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nvic_interrupt_enable(regs->nvic_int);
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@ -354,9 +354,9 @@ uart_write_byte(uint8_t uart, uint8_t b)
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uart_base = uart_regs[uart].base;
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/* Block if the TX FIFO is full */
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while(REG(uart_base | UART_FR) & UART_FR_TXFF);
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while(REG(uart_base + UART_FR) & UART_FR_TXFF);
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REG(uart_base | UART_DR) = b;
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REG(uart_base + UART_DR) = b;
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}
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/*---------------------------------------------------------------------------*/
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void
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@ -371,18 +371,18 @@ uart_isr(uint8_t uart)
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/* Store the current MIS and clear all flags early, except the RTM flag.
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* This will clear itself when we read out the entire FIFO contents */
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mis = REG(uart_base | UART_MIS) & 0x0000FFFF;
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mis = REG(uart_base + UART_MIS) & 0x0000FFFF;
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REG(uart_base | UART_ICR) = 0x0000FFBF;
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REG(uart_base + UART_ICR) = 0x0000FFBF;
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if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
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while(!(REG(uart_base | UART_FR) & UART_FR_RXFE)) {
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while(!(REG(uart_base + UART_FR) & UART_FR_RXFE)) {
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if(input_handler[uart] != NULL) {
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input_handler[uart]((unsigned char)(REG(uart_base | UART_DR) & 0xFF));
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input_handler[uart]((unsigned char)(REG(uart_base + UART_DR) & 0xFF));
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} else {
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/* To prevent an Overrun Error, we need to flush the FIFO even if we
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* don't have an input_handler. Use mis as a data trash can */
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mis = REG(uart_base | UART_DR);
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mis = REG(uart_base + UART_DR);
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}
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}
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} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {
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