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Use additive offsets

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OR-ing an offset to a base address instead of adding it is dangerous
because it can only work if the base address is aligned enough for the
offset.

Moreover, if the base address or the offset has a value unknown at
compile time, then the assembly instructions dedicated to 'base +
offset' addressing on most CPUs can't be emitted by the compiler because
this would require the alignment of the base address against the offset
to be known in order to optimize 'base | offset' into 'base + offset'.
In that case, the compiler has to emit more instructions in order to
compute 'base | offset' on most CPUs, e.g. on ARM, which means larger
binary size and slower execution.

Hence, replace all occurrences of 'base | offset' with 'base + offset'.
This must become a coding rule.

Here are the results for the cc2538-demo example:
 - Compilation of uart_init():
    * before:
        REG(regs->base | UART_CC) = 0;
        200b78:	f446 637c 	orr.w	r3, r6, #4032	; 0xfc0
        200b7c:	f043 0308 	orr.w	r3, r3, #8
        200b80:	2200      	movs	r2, #0
        200b82:	601a      	str	r2, [r3, #0]

    * now:
        REG(regs->base + UART_CC) = 0;
        200b7a:	2300      	movs	r3, #0
        200b7c:	f8c4 3fc8 	str.w	r3, [r4, #4040]	; 0xfc8

 - Size of the .text section:
    * before:	0x4c7c
    * now:	0x4c28
    * saved:	84 bytes

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This commit is contained in:
Benoît Thébaudeau 2015-03-28 17:16:17 +01:00
parent c76316adf2
commit 19fd7a3551
7 changed files with 65 additions and 65 deletions
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14
cpu/cc2538/clock.c
View file

@ -96,17 +96,17 @@ clock_init(void)
REG(SYS_CTRL_RCGCGPT) |= SYS_CTRL_RCGCGPT_GPT0;
/* Make sure GPT0 is off */
REG(GPT_0_BASE | GPTIMER_CTL) = 0;
REG(GPT_0_BASE + GPTIMER_CTL) = 0;
/* 16-bit */
REG(GPT_0_BASE | GPTIMER_CFG) = 0x04;
REG(GPT_0_BASE + GPTIMER_CFG) = 0x04;
/* One-Shot, Count Down, No Interrupts */
REG(GPT_0_BASE | GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
REG(GPT_0_BASE + GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
/* Prescale by 16 (thus, value 15 in TAPR) */
REG(GPT_0_BASE | GPTIMER_TAPR) = 0x0F;
REG(GPT_0_BASE + GPTIMER_TAPR) = 0x0F;
}
/*---------------------------------------------------------------------------*/
CCIF clock_time_t
@ -144,11 +144,11 @@ clock_wait(clock_time_t i)
void
clock_delay_usec(uint16_t dt)
{
REG(GPT_0_BASE | GPTIMER_TAILR) = dt;
REG(GPT_0_BASE | GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
REG(GPT_0_BASE + GPTIMER_TAILR) = dt;
REG(GPT_0_BASE + GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
/* One-Shot mode: TAEN will be cleared when the timer reaches 0 */
while(REG(GPT_0_BASE | GPTIMER_CTL) & GPTIMER_CTL_TAEN);
while(REG(GPT_0_BASE + GPTIMER_CTL) & GPTIMER_CTL_TAEN);
}
/*---------------------------------------------------------------------------*/
/**