Adds support for ADF7023 sub-GHz radio from Analog Devices and RL78 series MCU from Renesas.
This example platform for this port is the EVAL-ADF7XXXMB4Z w/ radio
daughter cards:
http://www.analog.com/en/evaluation/eval-adf7023/eb.html
See the platform readme for usage and platform information:
https://github.com/contiki-os/contiki/tree/master/platform/eval-adf7xxxmb4z/readme.md
All files provided by Analog Devices for this port are released under
the same license as Contiki and copyright Analog Devices Inc. per
agreement between Redwire Consulting, LLC and Analog Devices Inc. (SOW 08122013)
This commit is contained in:
Ian Martin
parent
e90af44ca7
commit
174d4dd80c
34 changed files with 11483 additions and 425 deletions
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@ -1,50 +1,66 @@
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/***************************************************************************//**
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* @file Communication.c
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* @brief Implementation of the Communication Driver for RL78G14 processor.
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* @author DBogdan (dragos.bogdan@analog.com)
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********************************************************************************
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* Copyright 2012(c) Analog Devices, Inc.
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*
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/*
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* Copyright (c) 2014, Analog Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
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* distribution.
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* - Neither the name of Analog Devices, Inc. nor the names of its
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* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
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* - The use of this software may or may not infringe the patent rights
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* of one or more patent holders. This license does not release you
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* from the requirement that you obtain separate licenses from these
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* patent holders to use this software.
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* - Use of the software either in source or binary form, must be run
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* on or directly connected to an Analog Devices Inc. component.
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*
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* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************
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* SVN Revision: $WCREV$
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*******************************************************************************/
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \author Dragos Bogdan <Dragos.Bogdan@Analog.com>, Ian Martin <martini@redwirellc.com>
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*/
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/******************************************************************************/
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/***************************** Include Files **********************************/
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/******************************************************************************/
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#include <stdint.h>
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#include "rl78.h"
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#include "Communication.h" /* Communication definitions */
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#include "RDKRL78G14.h" /* RDKRL78G14 definitions */
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#ifndef NOP
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#define NOP asm ("nop")
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#endif
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/* Enable interrupts: */
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#ifndef EI
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#ifdef __GNUC__
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#define EI asm ("ei");
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#else
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#define EI __enable_interrupt();
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#endif
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#endif
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#undef BIT
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#define BIT(n) (1 << (n))
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#define CLK_SCALER (0x4)
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#define SCALED_CLK (f_CLK / (1 << CLK_SCALER))
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#define BITBANG_SPI 1
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char IICA0_Flag;
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@ -57,8 +73,7 @@ char IICA0_Flag;
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*
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* @return None.
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*******************************************************************************/
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#pragma vector = INTIICA0_vect
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__interrupt static void
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/*__interrupt */ static void
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IICA0_Interrupt(void)
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{
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IICA0_Flag = 1;
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@ -87,25 +102,40 @@ IICA0_Interrupt(void)
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* -1 - if initialization was unsuccessful.
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*******************************************************************************/
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char
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SPI_Init(char lsbFirst,
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SPI_Init(enum CSI_Bus bus,
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char lsbFirst,
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long clockFreq,
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char clockPol,
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char clockEdg)
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{
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long mckFreq = 32000000;
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#if BITBANG_SPI
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PIOR5 = 1; /* Move SPI/I2C/UART functions from Port 0 pins 2-4 to Port 8. */
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/* Configure SCLK as an output. */
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PM0 &= ~BIT(4);
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POM0 &= ~BIT(4);
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/* Configure MOSI as an output: */
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PM0 &= ~BIT(2);
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POM0 &= ~BIT(2);
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PMC0 &= ~BIT(2);
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/* Configure MISO as an input: */
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PM0 |= BIT(3);
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PMC0 &= ~BIT(3);
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#else
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char sdrValue = 0;
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char delay = 0;
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uint16_t scr;
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uint8_t shift;
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/* Configure the CS pins. */
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PMOD1_CS_OUT;
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PMOD1_CS_HIGH;
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PMOD2_CS_OUT;
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PMOD2_CS_HIGH;
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ST7579_CS_OUT;
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ST7579_CS_HIGH;
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PIOR5 = 0; /* Keep SPI functions on Port 0 pins 2-4. */
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/* Enable input clock supply. */
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SAU1EN = 1;
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if(bus <= CSI11) {
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SAU0EN = 1;
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} else { SAU1EN = 1;
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}
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/* After setting the SAUmEN bit to 1, be sure to set serial clock select
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register m (SPSm) after 4 or more fCLK clocks have elapsed. */
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@ -115,36 +145,195 @@ SPI_Init(char lsbFirst,
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NOP;
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/* Select the fCLK as input clock. */
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SPS1 = 0x0000;
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if(bus <= CSI11) {
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SPS0 = (CLK_SCALER << 4) | CLK_SCALER; /* TODO: kludge */
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} else { SPS1 = (CLK_SCALER << 4) | CLK_SCALER; /* TODO: kludge */
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}
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/* Select the CSI operation mode. */
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SMR11 = 0x0020;
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switch(bus) {
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case CSI00: SMR00 = 0x0020;
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break;
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case CSI01: SMR01 = 0x0020;
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break;
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case CSI10: SMR02 = 0x0020;
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break;
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case CSI11: SMR03 = 0x0020;
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break;
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case CSI20: SMR10 = 0x0020;
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break;
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case CSI21: SMR11 = 0x0020;
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break;
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case CSI30: SMR12 = 0x0020;
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break;
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case CSI31: SMR13 = 0x0020;
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break;
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}
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clockPol = 1 - clockPol;
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SCR11 = (clockEdg << 13) |
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scr = (clockEdg << 13) |
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(clockPol << 12) |
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0xC000 | /* Operation mode: Transmission/reception. */
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0x0007; /* 8-bit data length. */
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switch(bus) {
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case CSI00: SCR00 = scr;
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break;
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case CSI01: SCR01 = scr;
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break;
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case CSI10: SCR02 = scr;
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break;
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case CSI11: SCR03 = scr;
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break;
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case CSI20: SCR10 = scr;
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break;
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case CSI21: SCR11 = scr;
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break;
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case CSI30: SCR12 = scr;
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break;
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case CSI31: SCR13 = scr;
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break;
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}
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/* clockFreq = mckFreq / (sdrValue * 2 + 2) */
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sdrValue = mckFreq / (2 * clockFreq) - 1;
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SDR11 = sdrValue << 9;
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sdrValue = SCALED_CLK / (2 * clockFreq) - 1;
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sdrValue <<= 9;
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switch(bus) {
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case CSI00: SDR00 = sdrValue;
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break;
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case CSI01: SDR01 = sdrValue;
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break;
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case CSI10: SDR02 = sdrValue;
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break;
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case CSI11: SDR03 = sdrValue;
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break;
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case CSI20: SDR10 = sdrValue;
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break;
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case CSI21: SDR11 = sdrValue;
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break;
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case CSI30: SDR12 = sdrValue;
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break;
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case CSI31: SDR13 = sdrValue;
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break;
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}
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/* Set the clock and data initial level. */
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clockPol = 1 - clockPol;
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SO1 &= ~0x0202;
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SO1 |= (clockPol << 9) |
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(clockPol << 1);
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shift = bus & 0x3;
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if(bus <= CSI11) {
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SO0 &= ~(0x0101 << shift);
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SO0 |= ((clockPol << 8) | clockPol) << shift;
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} else {
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SO1 &= ~(0x0101 << shift);
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SO1 |= ((clockPol << 8) | clockPol) << shift;
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}
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/* Enable output for serial communication operation. */
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SOE1 |= 0x0002;
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switch(bus) {
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case CSI00: SOE0 |= BIT(0);
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break;
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case CSI01: SOE0 |= BIT(1);
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break;
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case CSI10: SOE0 |= BIT(2);
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break;
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case CSI11: SOE0 |= BIT(3);
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break;
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case CSI20: SOE1 |= BIT(0);
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break;
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case CSI21: SOE1 |= BIT(1);
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break;
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case CSI30: SOE1 |= BIT(2);
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break;
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case CSI31: SOE1 |= BIT(3);
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break;
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}
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/* Configure the MISO pin as input. */
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PM7 |= 0x02;
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switch(bus) {
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case CSI00:
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/* SO00 output: */
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P1 |= BIT(2);
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PM1 &= ~BIT(2);
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/* Configure SCLK and MOSI pins as output. */
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P7 |= 0x05;
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PM7 &= ~0x05;
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/* SI00 input: */
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PM1 |= BIT(1);
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/* SCK00N output: */
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P1 |= BIT(0);
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PM1 &= ~BIT(0);
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break;
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case CSI01:
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/* SO01 output: */
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P7 |= BIT(3);
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PM7 &= ~BIT(3);
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/* SI01 input: */
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PM7 |= BIT(4);
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/* SCK01 output: */
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P7 |= BIT(5);
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PM7 &= ~BIT(5);
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break;
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case CSI10:
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PMC0 &= ~BIT(2); /* Disable analog input on SO10. */
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/* SO10 output: */
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P0 |= BIT(2);
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PM0 &= ~BIT(2);
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/* SI10 input: */
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PM0 |= BIT(3);
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/* SCK10N output: */
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P0 |= BIT(4);
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PM0 &= ~BIT(4);
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break;
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case CSI11:
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/* SO11 output: */
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P5 |= BIT(1);
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PM5 &= ~BIT(1);
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/* SI11 input: */
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PM5 |= BIT(0);
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/* SCK11 output: */
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P3 |= BIT(0);
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PM3 &= ~BIT(0);
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break;
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case CSI20:
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/* SO20 output: */
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P1 |= BIT(3);
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PM1 &= ~BIT(3);
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/* SI20 input: */
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PM1 |= BIT(4);
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/* SCK20 output: */
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P1 |= BIT(5);
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PM1 &= ~BIT(5);
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break;
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case CSI21:
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/* SO21 output: */
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P7 |= BIT(2);
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PM7 &= ~BIT(2);
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/* SI21 input: */
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PM7 |= BIT(1);
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/* SCK21 output: */
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P7 |= BIT(0);
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PM7 &= ~BIT(0);
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break;
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case CSI30:
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/* TODO: not supported */
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break;
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case CSI31:
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/* TODO: not supported */
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break;
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}
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/* Wait for the changes to take place. */
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for(delay = 0; delay < 50; delay++) {
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@ -152,7 +341,44 @@ SPI_Init(char lsbFirst,
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}
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/* Set the SEmn bit to 1 and enter the communication wait status */
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SS1 |= 0x0002;
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switch(bus) {
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case CSI00: SS0 = BIT(0);
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break;
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case CSI01: SS0 = BIT(1);
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break;
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case CSI10: SS0 = BIT(2);
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break;
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case CSI11: SS0 = BIT(3);
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break;
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case CSI20: SS1 = BIT(0);
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break;
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case CSI21: SS1 = BIT(1);
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break;
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case CSI30: SS1 = BIT(2);
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break;
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case CSI31: SS1 = BIT(3);
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break;
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}
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/* Sanity check: */
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if(bus == CSI10) {
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/* MOSI: */
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PIOR5 = 0;
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PMC02 = 0;
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PM02 = 0;
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P02 = 1;
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/* MISO: */
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PIOR5 = 0;
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PMC03 = 0;
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PM03 = 1;
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/* SCLK: */
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PIOR5 = 0;
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PM04 = 0;
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P04 = 1;
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}
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#endif
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return 0;
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}
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|
|
@ -165,8 +391,10 @@ SPI_Init(char lsbFirst,
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*
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* @return Number of written bytes.
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*******************************************************************************/
|
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#if 0
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char
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SPI_Write(char slaveDeviceId,
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SPI_Write(enum CSI_Bus bus,
|
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char slaveDeviceId,
|
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unsigned char *data,
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char bytesNumber)
|
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{
|
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|
|
@ -175,43 +403,84 @@ SPI_Write(char slaveDeviceId,
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unsigned short originalSCR = 0;
|
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unsigned short originalSO1 = 0;
|
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|
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if(slaveDeviceId == 1) {
|
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PMOD1_CS_LOW;
|
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}
|
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if(slaveDeviceId == 2) {
|
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PMOD2_CS_LOW;
|
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}
|
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if(slaveDeviceId == 3) {
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ST1 |= 0x0002;
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originalSO1 = SO1;
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originalSCR = SCR11;
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SO1 &= ~0x0202;
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SCR11 &= ~0x3000;
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SS1 |= 0x0002;
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ST7579_CS_LOW;
|
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volatile uint8_t *sio;
|
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volatile uint16_t *ssr;
|
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|
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switch(bus) {
|
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default:
|
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case CSI00: sio = &SIO00;
|
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ssr = &SSR00;
|
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break;
|
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case CSI01: sio = &SIO01;
|
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ssr = &SSR01;
|
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break;
|
||||
case CSI10: sio = &SIO10;
|
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ssr = &SSR02;
|
||||
break;
|
||||
case CSI11: sio = &SIO11;
|
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ssr = &SSR03;
|
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break;
|
||||
case CSI20: sio = &SIO20;
|
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ssr = &SSR10;
|
||||
break;
|
||||
case CSI21: sio = &SIO21;
|
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ssr = &SSR11;
|
||||
break;
|
||||
case CSI30: sio = &SIO30;
|
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ssr = &SSR12;
|
||||
break;
|
||||
case CSI31: sio = &SIO31;
|
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ssr = &SSR13;
|
||||
break;
|
||||
}
|
||||
|
||||
for(byte = 0; byte < bytesNumber; byte++) {
|
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SIO21 = data[byte];
|
||||
*sio = data[byte];
|
||||
NOP;
|
||||
while(SSR11 & 0x0040) ;
|
||||
read = SIO21;
|
||||
}
|
||||
if(slaveDeviceId == 1) {
|
||||
PMOD1_CS_HIGH;
|
||||
}
|
||||
if(slaveDeviceId == 2) {
|
||||
PMOD2_CS_HIGH;
|
||||
}
|
||||
if(slaveDeviceId == 3) {
|
||||
ST7579_CS_HIGH;
|
||||
ST1 |= 0x0002;
|
||||
SO1 = originalSO1;
|
||||
SCR11 = originalSCR;
|
||||
SS1 |= 0x0002;
|
||||
while(*ssr & 0x0040) ;
|
||||
read = *sio;
|
||||
}
|
||||
|
||||
return bytesNumber;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BITBANG_SPI
|
||||
#define sclk_low() (P0 &= ~BIT(4))
|
||||
#define sclk_high() (P0 |= BIT(4))
|
||||
#define mosi_low() (P0 &= ~BIT(2))
|
||||
#define mosi_high() (P0 |= BIT(2))
|
||||
#define read_miso() (P0bits.bit3)
|
||||
|
||||
static unsigned char
|
||||
spi_byte_exchange(unsigned char tx)
|
||||
{
|
||||
unsigned char rx = 0, n = 0;
|
||||
|
||||
sclk_low();
|
||||
|
||||
for(n = 0; n < 8; n++) {
|
||||
if(tx & 0x80) {
|
||||
mosi_high();
|
||||
} else { mosi_low();
|
||||
}
|
||||
|
||||
/* The slave samples MOSI at the rising-edge of SCLK. */
|
||||
sclk_high();
|
||||
|
||||
rx <<= 1;
|
||||
rx |= read_miso();
|
||||
|
||||
tx <<= 1;
|
||||
|
||||
/* The slave changes the value of MISO at the falling-edge of SCLK. */
|
||||
sclk_low();
|
||||
}
|
||||
|
||||
return rx;
|
||||
}
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief Reads data from SPI.
|
||||
*
|
||||
|
|
@ -223,48 +492,64 @@ SPI_Write(char slaveDeviceId,
|
|||
* @return Number of read bytes.
|
||||
*******************************************************************************/
|
||||
char
|
||||
SPI_Read(char slaveDeviceId,
|
||||
SPI_Read(enum CSI_Bus bus,
|
||||
char slaveDeviceId,
|
||||
unsigned char *data,
|
||||
char bytesNumber)
|
||||
{
|
||||
#if BITBANG_SPI
|
||||
unsigned char n = 0;
|
||||
for(n = 0; n < bytesNumber; n++) {
|
||||
data[n] = spi_byte_exchange(data[n]);
|
||||
}
|
||||
#else
|
||||
char byte = 0;
|
||||
unsigned short originalSCR = 0;
|
||||
unsigned short originalSO1 = 0;
|
||||
|
||||
if(slaveDeviceId == 1) {
|
||||
PMOD1_CS_LOW;
|
||||
}
|
||||
if(slaveDeviceId == 2) {
|
||||
PMOD2_CS_LOW;
|
||||
}
|
||||
if(slaveDeviceId == 3) {
|
||||
ST1 |= 0x0002;
|
||||
originalSO1 = SO1;
|
||||
originalSCR = SCR11;
|
||||
SO1 &= ~0x0202;
|
||||
SCR11 &= ~0x3000;
|
||||
SS1 |= 0x0002;
|
||||
ST7579_CS_LOW;
|
||||
volatile uint8_t *sio;
|
||||
volatile uint16_t *ssr;
|
||||
char dummy;
|
||||
|
||||
switch(bus) {
|
||||
default:
|
||||
case CSI00: sio = &SIO00;
|
||||
ssr = &SSR00;
|
||||
break;
|
||||
case CSI01: sio = &SIO01;
|
||||
ssr = &SSR01;
|
||||
break;
|
||||
case CSI10: sio = &SIO10;
|
||||
ssr = &SSR02;
|
||||
break;
|
||||
case CSI11: sio = &SIO11;
|
||||
ssr = &SSR03;
|
||||
break;
|
||||
case CSI20: sio = &SIO20;
|
||||
ssr = &SSR10;
|
||||
break;
|
||||
case CSI21: sio = &SIO21;
|
||||
ssr = &SSR11;
|
||||
break;
|
||||
case CSI30: sio = &SIO30;
|
||||
ssr = &SSR12;
|
||||
break;
|
||||
case CSI31: sio = &SIO31;
|
||||
ssr = &SSR13;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Flush the receive buffer: */
|
||||
while(*ssr & 0x0020) dummy = *sio;
|
||||
(void)dummy;
|
||||
|
||||
for(byte = 0; byte < bytesNumber; byte++) {
|
||||
SIO21 = data[byte];
|
||||
*sio = data[byte];
|
||||
NOP;
|
||||
while(SSR11 & 0x0040) ;
|
||||
data[byte] = SIO21;
|
||||
}
|
||||
if(slaveDeviceId == 1) {
|
||||
PMOD1_CS_HIGH;
|
||||
}
|
||||
if(slaveDeviceId == 2) {
|
||||
PMOD2_CS_HIGH;
|
||||
}
|
||||
if(slaveDeviceId == 3) {
|
||||
ST7579_CS_HIGH;
|
||||
ST1 |= 0x0002;
|
||||
SO1 = originalSO1;
|
||||
SCR11 = originalSCR;
|
||||
SS1 |= 0x0002;
|
||||
while(*ssr & 0x0040) ;
|
||||
data[byte] = *sio;
|
||||
}
|
||||
#endif
|
||||
|
||||
return bytesNumber;
|
||||
}
|
||||
|
|
@ -284,6 +569,8 @@ I2C_Init(long clockFreq)
|
|||
unsigned char wlValue = 0;
|
||||
unsigned char whValue = 0;
|
||||
|
||||
(void)IICA0_Interrupt; /* Prevent an unused-function warning. */
|
||||
|
||||
/* Enable interrupts */
|
||||
EI;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue