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Merge pull request #825 from alignan/i2c_changes

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Add function to change I2C baudrate and push relevant configuration valu...
This commit is contained in:
Nicolas Tsiftes 2014-10-21 06:46:55 +02:00
parent 0d39ee96ad ef6c351d0c
commit 10d444637e
6 changed files with 200 additions and 231 deletions
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14
examples/z1/test-light-ziglet.c
View file

@ -42,22 +42,13 @@
#include "dev/i2cmaster.h" #include "dev/i2cmaster.h"
#include "dev/light-ziglet.h" #include "dev/light-ziglet.h"
#if 1 #if 1
#define PRINTF(...) printf(__VA_ARGS__) #define PRINTF(...) printf(__VA_ARGS__)
#else #else
#define PRINTF(...) #define PRINTF(...)
#endif #endif
#define SENSOR_READ_INTERVAL (CLOCK_SECOND / 2)
#if 0
#define PRINTFDEBUG(...) printf(__VA_ARGS__)
#else
#define PRINTFDEBUG(...)
#endif
#define SENSOR_READ_INTERVAL (CLOCK_SECOND)
PROCESS(test_process, "Test light ziglet process"); PROCESS(test_process, "Test light ziglet process");
AUTOSTART_PROCESSES(&test_process); AUTOSTART_PROCESSES(&test_process);
@ -70,7 +61,10 @@ PROCESS_THREAD(test_process, ev, data)
uint16_t light; uint16_t light;
/* Initialize driver and set a slower data rate */
light_ziglet_init(); light_ziglet_init();
i2c_setrate(I2C_PRESC_100KHZ_LSB, I2C_PRESC_100KHZ_MSB);
while(1) { while(1) {
etimer_set(&et, SENSOR_READ_INTERVAL); etimer_set(&et, SENSOR_READ_INTERVAL);

236
platform/z1/dev/i2cmaster.c
View file

@ -41,98 +41,90 @@
#include "i2cmaster.h" #include "i2cmaster.h"
#include "isr_compat.h" #include "isr_compat.h"
signed char tx_byte_ctr, rx_byte_ctr; signed char tx_byte_ctr, rx_byte_ctr;
unsigned char rx_buf[2]; unsigned char rx_buf[2];
unsigned char* tx_buf_ptr; unsigned char *tx_buf_ptr;
unsigned char* rx_buf_ptr; unsigned char *rx_buf_ptr;
unsigned char receive_data; unsigned char receive_data;
unsigned char transmit_data1; unsigned char transmit_data1;
unsigned char transmit_data2; unsigned char transmit_data2;
volatile unsigned int i; // volatile to prevent optimization unsigned char prescale_lsb = I2C_PRESC_Z1_LSB;
unsigned char prescale_msb = I2C_PRESC_Z1_MSB;
volatile unsigned int i; /* volatile to prevent optimization */
//------------------------------------------------------------------------------ /* ------------------------------------------------------------------------------
// void i2c_receiveinit(unsigned char slave_address, * Change the data rate prior initializing transmission or reception
// unsigned char prescale) * ----------------------------------------------------------------------------- */
//
// This function initializes the USCI module for master-receive operation.
//
// IN: unsigned char slave_address => Slave Address
// unsigned char prescale => SCL clock adjustment
//-----------------------------------------------------------------------------
void void
i2c_receiveinit(uint8_t slave_address) { i2c_setrate(uint8_t p_lsb, uint8_t p_msb)
UCB1CTL1 = UCSWRST; // Enable SW reset {
UCB1CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode prescale_lsb = p_lsb;
UCB1CTL1 = UCSSEL_2 | UCSWRST; // Use SMCLK, keep SW reset prescale_lsb = p_msb;
UCB1BR0 = I2C_PRESC_400KHZ_LSB; // prescaler for 400 kHz data rate }
UCB1BR1 = I2C_PRESC_400KHZ_MSB; /* ------------------------------------------------------------------------------
UCB1I2CSA = slave_address; // set slave address * This function initializes the USCI module for master-receive operation.
* ----------------------------------------------------------------------------- */
UCB1CTL1 &= ~UCTR; // I2C Receiver void
i2c_receiveinit(uint8_t slave_address)
UCB1CTL1 &= ~UCSWRST; // Clear SW reset, resume operation {
UCB1CTL1 = UCSWRST; /* Enable SW reset */
UCB1CTL0 = UCMST + UCMODE_3 + UCSYNC; /* I2C Master, synchronous mode */
UCB1CTL1 = UCSSEL_2 | UCSWRST; /* Use SMCLK, keep SW reset */
UCB1BR0 = prescale_lsb; /* prescaler (default 400 kHz) */
UCB1BR1 = prescale_msb;
UCB1I2CSA = slave_address; /* set slave address */
UCB1CTL1 &= ~UCTR; /* I2C Receiver */
UCB1CTL1 &= ~UCSWRST; /* Clear SW reset, resume operation */
UCB1I2CIE = UCNACKIE; UCB1I2CIE = UCNACKIE;
#if I2C_RX_WITH_INTERRUPT #if I2C_RX_WITH_INTERRUPT
UC1IE = UCB1RXIE; // Enable RX interrupt if desired UC1IE = UCB1RXIE; /* Enable RX interrupt if desired */
#endif #endif
} }
/* ------------------------------------------------------------------------------
//------------------------------------------------------------------------------ * Initializes USCI for master-transmit operation.
// void i2c_transmitinit(unsigned char slave_address, * ------------------------------------------------------------------------------ */
// unsigned char prescale)
//
// Initializes USCI for master-transmit operation.
//
// IN: unsigned char slave_address => Slave Address
// unsigned char prescale => SCL clock adjustment
//------------------------------------------------------------------------------
void void
i2c_transmitinit(uint8_t slave_address) { i2c_transmitinit(uint8_t slave_address)
UCB1CTL1 |= UCSWRST; // Enable SW reset {
UCB1CTL0 |= (UCMST | UCMODE_3 | UCSYNC); // I2C Master, synchronous mode UCB1CTL1 |= UCSWRST; /* Enable SW reset */
UCB1CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset UCB1CTL0 |= (UCMST | UCMODE_3 | UCSYNC); /* I2C Master, synchronous mode */
UCB1BR0 = I2C_PRESC_400KHZ_LSB; // prescaler for 400 kHz data rate UCB1CTL1 = UCSSEL_2 + UCSWRST; /* Use SMCLK, keep SW reset */
UCB1BR1 = I2C_PRESC_400KHZ_MSB; UCB1BR0 = prescale_lsb; /* prescaler (default 400 kHz) */
UCB1I2CSA = slave_address; // Set slave address UCB1BR1 = prescale_msb;
UCB1I2CSA = slave_address; /* Set slave address */
UCB1CTL1 &= ~UCSWRST; // Clear SW reset, resume operation UCB1CTL1 &= ~UCSWRST; /* Clear SW reset, resume operation */
UCB1I2CIE = UCNACKIE; UCB1I2CIE = UCNACKIE;
UC1IE = UCB1TXIE; // Enable TX ready interrupt UC1IE = UCB1TXIE; /* Enable TX ready interrupt */
} }
/* ------------------------------------------------------------------------------
//------------------------------------------------------------------------------ * This function is used to start an I2C communication in master-receiver mode WITHOUT INTERRUPTS
// void i2c_receive_n(unsigned char byte_ctr, unsigned char * rx_buf) * for more than 1 byte
// This function is used to start an I2C communication in master-receiver mode WITHOUT INTERRUPTS * ------------------------------------------------------------------------------ */
// for more than 1 byte
// IN: unsigned char byte_ctr => number of bytes to be read
// OUT: unsigned char rx_buf => receive data buffer
// OUT: int n_received => number of bytes read
//------------------------------------------------------------------------------
static volatile uint8_t rx_byte_tot = 0; static volatile uint8_t rx_byte_tot = 0;
uint8_t uint8_t
i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf) { i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf)
{
rx_byte_tot = byte_ctr; rx_byte_tot = byte_ctr;
rx_byte_ctr = byte_ctr; rx_byte_ctr = byte_ctr;
rx_buf_ptr = rx_buf; rx_buf_ptr = rx_buf;
while ((UCB1CTL1 & UCTXSTT) || (UCB1STAT & UCNACKIFG)) // Slave acks address or not? while((UCB1CTL1 & UCTXSTT) || (UCB1STAT & UCNACKIFG)) /* Slave acks address or not? */
PRINTFDEBUG ("____ UCTXSTT not clear OR NACK received\n"); PRINTFDEBUG("____ UCTXSTT not clear OR NACK received\n");
#if I2C_RX_WITH_INTERRUPT #if I2C_RX_WITH_INTERRUPT
PRINTFDEBUG(" RX Interrupts: YES \n"); PRINTFDEBUG(" RX Interrupts: YES \n");
// SPECIAL-CASE: Stop condition must be sent while receiving the 1st byte for 1-byte only read operations /* SPECIAL-CASE: Stop condition must be sent while receiving the 1st byte for 1-byte only read operations */
if(rx_byte_tot == 1){ // See page 537 of slau144e.pdf if(rx_byte_tot == 1) { /* See page 537 of slau144e.pdf */
dint(); dint();
UCB1CTL1 |= UCTXSTT; // I2C start condition UCB1CTL1 |= UCTXSTT; /* I2C start condition */
while(UCB1CTL1 & UCTXSTT) // Waiting for Start bit to clear while(UCB1CTL1 & UCTXSTT) /* Waiting for Start bit to clear */
PRINTFDEBUG ("____ STT clear wait\n"); PRINTFDEBUG("____ STT clear wait\n");
UCB1CTL1 |= UCTXSTP; // I2C stop condition UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
eint(); eint();
} } else { /* all other cases */
else{ // all other cases UCB1CTL1 |= UCTXSTT; /* I2C start condition */
UCB1CTL1 |= UCTXSTT; // I2C start condition
} }
return 0; return 0;
@ -141,98 +133,86 @@ i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf) {
PRINTFDEBUG(" RX Interrupts: NO \n"); PRINTFDEBUG(" RX Interrupts: NO \n");
UCB1CTL1 |= UCTXSTT; // I2C start condition UCB1CTL1 |= UCTXSTT; /* I2C start condition */
while (rx_byte_ctr > 0){ while(rx_byte_ctr > 0) {
if (UC1IFG & UCB1RXIFG) { // Waiting for Data if(UC1IFG & UCB1RXIFG) { /* Waiting for Data */
rx_buf[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF; rx_buf[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF;
rx_byte_ctr--; rx_byte_ctr--;
UC1IFG &= ~UCB1RXIFG; // Clear USCI_B1 RX int flag UC1IFG &= ~UCB1RXIFG; /* Clear USCI_B1 RX int flag */
n_received++; n_received++;
} }
} }
UCB1CTL1 |= UCTXSTP; // I2C stop condition UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
return n_received; return n_received;
#endif #endif
} }
/* ------------------------------------------------------------------------------
* This function is used to check if there is communication in progress.
//------------------------------------------------------------------------------ * ------------------------------------------------------------------------------ */
// uint8_t i2c_busy()
//
// This function is used to check if there is communication in progress.
//
// OUT: unsigned char => 0: I2C bus is idle,
// 1: communication is in progress
//------------------------------------------------------------------------------
uint8_t uint8_t
i2c_busy(void) { i2c_busy(void)
return (UCB1STAT & UCBBUSY); {
return UCB1STAT & UCBBUSY;
} }
/*----------------------------------------------------------------------------
/*----------------------------------------------------------------------------*/ * Setup ports and pins for I2C use.
/* Setup ports and pins for I2C use. */ * ------------------------------------------------------------------------------ */
void void
i2c_enable(void) { i2c_enable(void)
I2C_PxSEL |= (I2C_SDA | I2C_SCL); // Secondary function (USCI) selected {
I2C_PxSEL2 |= (I2C_SDA | I2C_SCL); // Secondary function (USCI) selected I2C_PxSEL |= (I2C_SDA | I2C_SCL); /* Secondary function (USCI) selected */
I2C_PxDIR |= I2C_SCL; // SCL is output (not needed?) I2C_PxSEL2 |= (I2C_SDA | I2C_SCL); /* Secondary function (USCI) selected */
I2C_PxDIR &= ~I2C_SDA; // SDA is input (not needed?) I2C_PxDIR |= I2C_SCL; /* SCL is output (not needed?) */
I2C_PxREN |= (I2C_SDA | I2C_SCL); // Activate internal pull-up/-down resistors I2C_PxDIR &= ~I2C_SDA; /* SDA is input (not needed?) */
I2C_PxOUT |= (I2C_SDA | I2C_SCL); // Select pull-up resistors I2C_PxREN |= (I2C_SDA | I2C_SCL); /* Activate internal pull-up/-down resistors */
I2C_PxOUT |= (I2C_SDA | I2C_SCL); /* Select pull-up resistors */
} }
void void
i2c_disable(void) { i2c_disable(void)
I2C_PxSEL &= ~(I2C_SDA | I2C_SCL); // GPIO function selected {
I2C_PxSEL2 &= ~(I2C_SDA | I2C_SCL); // GPIO function selected I2C_PxSEL &= ~(I2C_SDA | I2C_SCL); /* GPIO function selected */
I2C_PxREN &= ~(I2C_SDA | I2C_SCL); // Deactivate internal pull-up/-down resistors I2C_PxSEL2 &= ~(I2C_SDA | I2C_SCL); /* GPIO function selected */
I2C_PxOUT &= ~(I2C_SDA | I2C_SCL); // Select pull-up resistors I2C_PxREN &= ~(I2C_SDA | I2C_SCL); /* Deactivate internal pull-up/-down resistors */
I2C_PxOUT &= ~(I2C_SDA | I2C_SCL); /* Select pull-up resistors */
} }
/* ------------------------------------------------------------------------------
/*----------------------------------------------------------------------------*/ * This function is used to start an I2C communication in master-transmit mode.
//------------------------------------------------------------------------------ * ------------------------------------------------------------------------------ */
// void i2c_transmit_n(unsigned char byte_ctr, unsigned char *field)
//
// This function is used to start an I2C communication in master-transmit mode.
//
// IN: unsigned char byte_ctr => number of bytes to be transmitted
// unsigned char *tx_buf => Content to transmit. Read and transmitted from [0] to [byte_ctr]
//------------------------------------------------------------------------------
static volatile uint8_t tx_byte_tot = 0; static volatile uint8_t tx_byte_tot = 0;
void void
i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf) { i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf)
{
tx_byte_tot = byte_ctr; tx_byte_tot = byte_ctr;
tx_byte_ctr = byte_ctr; tx_byte_ctr = byte_ctr;
tx_buf_ptr = tx_buf; tx_buf_ptr = tx_buf;
UCB1CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition UCB1CTL1 |= UCTR + UCTXSTT; /* I2C TX, start condition */
} }
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
ISR(USCIAB1TX, i2c_tx_interrupt) ISR(USCIAB1TX, i2c_tx_interrupt)
{ {
// TX Part /* TX Part */
if (UC1IFG & UCB1TXIFG) { // TX int. condition if(UC1IFG & UCB1TXIFG) { /* TX int. condition */
if (tx_byte_ctr == 0) { if(tx_byte_ctr == 0) {
UCB1CTL1 |= UCTXSTP; // I2C stop condition UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
UC1IFG &= ~UCB1TXIFG; // Clear USCI_B1 TX int flag UC1IFG &= ~UCB1TXIFG; /* Clear USCI_B1 TX int flag */
} } else {
else {
UCB1TXBUF = tx_buf_ptr[tx_byte_tot - tx_byte_ctr]; UCB1TXBUF = tx_buf_ptr[tx_byte_tot - tx_byte_ctr];
tx_byte_ctr--; tx_byte_ctr--;
} }
} }
// RX Part /* RX Part */
#if I2C_RX_WITH_INTERRUPT #if I2C_RX_WITH_INTERRUPT
else if (UC1IFG & UCB1RXIFG){ // RX int. condition else if(UC1IFG & UCB1RXIFG) { /* RX int. condition */
rx_buf_ptr[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF; rx_buf_ptr[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF;
rx_byte_ctr--; rx_byte_ctr--;
if (rx_byte_ctr == 1){ //stop condition should be set before receiving last byte if(rx_byte_ctr == 1) { /* stop condition should be set before receiving last byte */
// Only for 1-byte transmissions, STOP is handled in receive_n_int /* Only for 1-byte transmissions, STOP is handled in receive_n_int */
if (rx_byte_tot != 1) if(rx_byte_tot != 1) {
UCB1CTL1 |= UCTXSTP; // I2C stop condition UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
UC1IFG &= ~UCB1RXIFG; // Clear USCI_B1 RX int flag. XXX Just in case, check if necessary }
UC1IFG &= ~UCB1RXIFG; /* Clear USCI_B1 RX int flag. XXX Just in case, check if necessary */
} }
} }
#endif #endif

29
platform/z1/dev/i2cmaster.h
View file

@ -53,32 +53,7 @@ void i2c_transmitinit(uint8_t slave_address);
void i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf); void i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf);
uint8_t i2c_busy(void); uint8_t i2c_busy(void);
void i2c_setrate(uint8_t p_lsb, uint8_t p_msb);
//XXX Should these defines be in the contiki-conf.h to make it more platform-independent?
#define I2C_PxDIR P5DIR
#define I2C_PxIN P5IN
#define I2C_PxOUT P5OUT
#define I2C_PxSEL P5SEL
#define I2C_PxSEL2 P5SEL2
#define I2C_PxREN P5REN
#define I2C_SDA (1 << 1) //SDA == P5.1
#define I2C_SCL (1 << 2) //SCL == P5.2
#define I2C_PRESC_1KHZ_LSB 0x00
#define I2C_PRESC_1KHZ_MSB 0x20
#define I2C_PRESC_100KHZ_LSB 0x50
#define I2C_PRESC_100KHZ_MSB 0x00
#define I2C_PRESC_400KHZ_LSB 0x14
#define I2C_PRESC_400KHZ_MSB 0x00
// I2C configuration with RX interrupts
#ifdef I2C_CONF_RX_WITH_INTERRUPT
#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT // XXX Move I2C_CONF_RX_WITH_INTERRUPT to contiki-conf.h or platform-conf.h
#else /* I2C_CONF_RX_WITH_INTERRUPT */
#define I2C_RX_WITH_INTERRUPT 1
#endif /* I2C_CONF_RX_WITH_INTERRUPT */
#if 0 #if 0
#include <stdio.h> #include <stdio.h>
@ -87,4 +62,4 @@ uint8_t i2c_busy(void);
#define PRINTFDEBUG(...) #define PRINTFDEBUG(...)
#endif #endif
#endif /* #ifdef I2CMASTER_H_ */ #endif /* #ifdef I2CMASTER_H_ */

20
platform/z1/dev/light-ziglet.c
View file

@ -33,6 +33,7 @@
/** /**
* \file * \file
* Device drivers for light ziglet sensor in Zolertia Z1. * Device drivers for light ziglet sensor in Zolertia Z1.
* It is recommended to use with a 100KHz data rate
* \author * \author
* Antonio Lignan, Zolertia <alinan@zolertia.com> * Antonio Lignan, Zolertia <alinan@zolertia.com>
* Marcus Lundén, SICS <mlunden@sics.se> * Marcus Lundén, SICS <mlunden@sics.se>
@ -49,8 +50,6 @@
#define PRINTFDEBUG(...) #define PRINTFDEBUG(...)
#endif #endif
#warning LIGHT SENSOR ZIGLET IS CURRENTLY BROKEN
/* Bitmasks and bit flag variable for keeping track of tmp102 status. */ /* Bitmasks and bit flag variable for keeping track of tmp102 status. */
enum TSL2563_STATUSTYPES { enum TSL2563_STATUSTYPES {
/* must be a bit and not more, not using 0x00. */ /* must be a bit and not more, not using 0x00. */
@ -171,7 +170,7 @@ tsl2563_read_reg(uint8_t reg)
/* Receive the data */ /* Receive the data */
i2c_receiveinit(TSL2563_ADDR); i2c_receiveinit(TSL2563_ADDR);
while(i2c_busy()); while(i2c_busy());
i2c_receive_n(4, &buf[0]); i2c_receive_n(4, buf);
while(i2c_busy()); while(i2c_busy());
PRINTFDEBUG("\nb0 %u, b1 %u, b2 %u, b3 %u\n", buf[0], buf[1], buf[2], buf[3]); PRINTFDEBUG("\nb0 %u, b1 %u, b2 %u, b3 %u\n", buf[0], buf[1], buf[2], buf[3]);
@ -179,25 +178,18 @@ tsl2563_read_reg(uint8_t reg)
readBuf[0] = (buf[1] << 8 | (buf[0])); readBuf[0] = (buf[1] << 8 | (buf[0]));
readBuf[1] = (buf[3] << 8 | (buf[2])); readBuf[1] = (buf[3] << 8 | (buf[2]));
/* XXX Quick hack, was receiving dups bytes */ retVal = calculateLux(readBuf);
return retVal;
if(readBuf[0] == readBuf[1]) {
tsl2563_read_reg(TSL2563_READ);
return 0x00;
} else {
retVal = calculateLux(readBuf);
return retVal;
}
} }
uint16_t uint16_t
light_ziglet_on(void) light_ziglet_on(void)
{ {
uint16_t data; uint16_t data;
uint8_t regon[] = { 0x00, TSL2563_PWRN }; uint8_t regon = TSL2563_PWRN;
/* Turn on the sensor */ /* Turn on the sensor */
i2c_transmitinit(TSL2563_ADDR); i2c_transmitinit(TSL2563_ADDR);
while(i2c_busy()); while(i2c_busy());
i2c_transmit_n(2, regon); i2c_transmit_n(1, &regon);
while(i2c_busy()); while(i2c_busy());
data = (uint16_t)tsl2563_read_reg(TSL2563_READ); data = (uint16_t)tsl2563_read_reg(TSL2563_READ);
return data; return data;

14
platform/z1/dev/light-ziglet.h
View file

@ -43,35 +43,33 @@
#include <stdio.h> #include <stdio.h>
#include "i2cmaster.h" #include "i2cmaster.h"
/* -------------------------------------------------------------------------- */ /* Init the light ziglet sensor: ports, pins, I2C, interrupts */
/* Init the light ziglet sensor: ports, pins, I2C, interrupts (XXX none so far),
*/
void light_ziglet_init(void); void light_ziglet_init(void);
/* Write to a register. /* Write to a register.
args: args:
reg register to write to reg register to write to
val value to write val value to write
*/ */
void tsl2563_write_reg(uint8_t reg, uint16_t val); void tsl2563_write_reg(uint8_t reg, uint16_t val);
/* Read one register. /* Read one register.
args: args:
reg what register to read reg what register to read
returns the value of the read register returns the value of the read register
*/ */
uint16_t tsl2563_read_reg(uint8_t reg); uint16_t tsl2563_read_reg(uint8_t reg);
/* Takes a single light reading /* Takes a single light reading
args: none args: none
returns a lux value returns a lux value
*/ */
uint16_t light_ziglet_read(); uint16_t light_ziglet_read();
/* Calculates the lux values from the calibration table /* Calculates the lux values from the calibration table
args: raw values from sensor args: raw values from sensor
returns a lux value returns a lux value
*/ */
uint16_t calculateLux(uint16_t *readRaw); uint16_t calculateLux(uint16_t *readRaw);
/* Turns the light ziglet ON and polls the sensor for a light reading */ /* Turns the light ziglet ON and polls the sensor for a light reading */
@ -123,5 +121,3 @@ uint16_t light_ziglet_on(void);
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#endif /* ifndef LIGHT_ZIGLET_H_ */ #endif /* ifndef LIGHT_ZIGLET_H_ */

114
platform/z1/platform-conf.h
View file

@ -50,12 +50,11 @@
/* CPU target speed in Hz */ /* CPU target speed in Hz */
#define F_CPU 8000000uL /* 8MHz by default */ #define F_CPU 8000000uL /* 8MHz by default */
//Enric #define F_CPU 3900000uL /*2457600uL*/
/* Our clock resolution, this is the same as Unix HZ. */ /* Our clock resolution, this is the same as Unix HZ. */
#define CLOCK_CONF_SECOND 128UL #define CLOCK_CONF_SECOND 128UL
#define BAUD2UBR(baud) ((F_CPU/baud)) #define BAUD2UBR(baud) ((F_CPU / baud))
#define CCIF #define CCIF
#define CLIF #define CLIF
@ -67,21 +66,21 @@
#ifdef __IAR_SYSTEMS_ICC__ #ifdef __IAR_SYSTEMS_ICC__
#ifndef P1SEL2_ #ifndef P1SEL2_
#define P1SEL2_ (0x0041u) /* Port 1 Selection 2*/ #define P1SEL2_ (0x0041u) /* Port 1 Selection 2*/
DEFC( P1SEL2 , P1SEL2_) DEFC(P1SEL2, P1SEL2_)
#endif #endif
#ifndef P5SEL2_ #ifndef P5SEL2_
#define P5SEL2_ (0x0045u) /* Port 5 Selection 2*/ #define P5SEL2_ (0x0045u) /* Port 5 Selection 2*/
DEFC( P5SEL2 , P5SEL2_) DEFC(P5SEL2, P5SEL2_)
#endif #endif
#else /* __IAR_SYSTEMS_ICC__ */ #else /* __IAR_SYSTEMS_ICC__ */
#ifdef __GNUC__ #ifdef __GNUC__
#ifndef P1SEL2_ #ifndef P1SEL2_
#define P1SEL2_ 0x0041 /* Port 1 Selection 2*/ #define P1SEL2_ 0x0041 /* Port 1 Selection 2*/
sfrb(P1SEL2, P1SEL2_); sfrb(P1SEL2, P1SEL2_);
#endif #endif
#ifndef P5SEL2_ #ifndef P5SEL2_
#define P5SEL2_ 0x0045 /* Port 5 Selection 2*/ #define P5SEL2_ 0x0045 /* Port 5 Selection 2*/
sfrb(P5SEL2, P5SEL2_); sfrb(P5SEL2, P5SEL2_);
#endif #endif
#endif /* __GNUC__ */ #endif /* __GNUC__ */
#endif /* __IAR_SYSTEMS_ICC__ */ #endif /* __IAR_SYSTEMS_ICC__ */
@ -112,15 +111,14 @@ typedef unsigned long off_t;
#define LEDS_CONF_RED 0x10 #define LEDS_CONF_RED 0x10
#define LEDS_CONF_GREEN 0x40 #define LEDS_CONF_GREEN 0x40
#define LEDS_CONF_YELLOW 0x20 #define LEDS_CONF_YELLOW 0x20
#endif // Z1_IS_Z1SP #endif /* Z1_IS_Z1SP */
/* DCO speed resynchronization for more robust UART, etc. */ /* DCO speed resynchronization for more robust UART, etc. */
#define DCOSYNCH_CONF_ENABLED 0 #define DCOSYNCH_CONF_ENABLED 0
#define DCOSYNCH_CONF_PERIOD 30 #define DCOSYNCH_CONF_PERIOD 30
#define ROM_ERASE_UNIT_SIZE 512 #define ROM_ERASE_UNIT_SIZE 512
#define XMEM_ERASE_UNIT_SIZE (64*1024L) #define XMEM_ERASE_UNIT_SIZE (64 * 1024L)
#define CFS_CONF_OFFSET_TYPE long #define CFS_CONF_OFFSET_TYPE long
@ -136,19 +134,19 @@ typedef unsigned long off_t;
#define CFS_RAM_CONF_SIZE 4096 #define CFS_RAM_CONF_SIZE 4096
/* /*
* SPI bus configuration for the TMote Sky. * SPI bus configuration for the Z1 mote.
*/ */
/* SPI input/output registers. */ /* SPI input/output registers. */
#define SPI_TXBUF UCB0TXBUF #define SPI_TXBUF UCB0TXBUF
#define SPI_RXBUF UCB0RXBUF #define SPI_RXBUF UCB0RXBUF
/* USART0 Tx ready? */ /* USART0 Tx ready? */
#define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0) #define SPI_WAITFOREOTx() while((UCB0STAT & UCBUSY) != 0)
/* USART0 Rx ready? */ /* USART0 Rx ready? */
#define SPI_WAITFOREORx() while ((IFG2 & UCB0RXIFG) == 0) #define SPI_WAITFOREORx() while((IFG2 & UCB0RXIFG) == 0)
/* USART0 Tx buffer ready? */ /* USART0 Tx buffer ready? */
#define SPI_WAITFORTxREADY() while ((IFG2 & UCB0TXIFG) == 0) #define SPI_WAITFORTxREADY() while((IFG2 & UCB0TXIFG) == 0)
#define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */ #define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
#define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */ #define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
@ -157,24 +155,23 @@ typedef unsigned long off_t;
/* /*
* SPI bus - M25P80 external flash configuration. * SPI bus - M25P80 external flash configuration.
*/ */
//#define FLASH_PWR 3 /* P4.3 Output */ ALWAYS POWERED ON Z1 /* FLASH_PWR P4.3 Output ALWAYS POWERED ON Z1 */
#define FLASH_CS 4 /* P4.4 Output */ #define FLASH_CS 4 /* P4.4 Output */
#define FLASH_HOLD 7 /* P5.7 Output */ #define FLASH_HOLD 7 /* P5.7 Output */
/* Enable/disable flash access to the SPI bus (active low). */ /* Enable/disable flash access to the SPI bus (active low). */
#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) ) #define SPI_FLASH_ENABLE() (P4OUT &= ~BV(FLASH_CS))
#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) ) #define SPI_FLASH_DISABLE() (P4OUT |= BV(FLASH_CS))
#define SPI_FLASH_HOLD() ( P5OUT &= ~BV(FLASH_HOLD) )
#define SPI_FLASH_UNHOLD() ( P5OUT |= BV(FLASH_HOLD) )
#define SPI_FLASH_HOLD() (P5OUT &= ~BV(FLASH_HOLD))
#define SPI_FLASH_UNHOLD() (P5OUT |= BV(FLASH_HOLD))
/* /*
* SPI bus - CC2420 pin configuration. * SPI bus - CC2420 pin configuration.
*/ */
#define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */ #define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
/* P1.2 - Input: FIFOP from CC2420 */ /* P1.2 - Input: FIFOP from CC2420 */
#define CC2420_FIFOP_PORT(type) P1##type #define CC2420_FIFOP_PORT(type) P1##type
@ -188,7 +185,7 @@ typedef unsigned long off_t;
/* P4.1 - Input: SFD from CC2420 */ /* P4.1 - Input: SFD from CC2420 */
#define CC2420_SFD_PORT(type) P4##type #define CC2420_SFD_PORT(type) P4##type
#define CC2420_SFD_PIN 1 #define CC2420_SFD_PIN 1
/* P3.0 - Output: SPI Chip Select (CS_N) */ /* P3.0 - Output: SPI Chip Select (CS_N) */
#define CC2420_CSN_PORT(type) P3##type #define CC2420_CSN_PORT(type) P3##type
#define CC2420_CSN_PIN 0 #define CC2420_CSN_PIN 0
/* P4.5 - Output: VREG_EN to CC2420 */ /* P4.5 - Output: VREG_EN to CC2420 */
@ -198,7 +195,6 @@ typedef unsigned long off_t;
#define CC2420_RESET_PORT(type) P4##type #define CC2420_RESET_PORT(type) P4##type
#define CC2420_RESET_PIN 6 #define CC2420_RESET_PIN 6
#define CC2420_IRQ_VECTOR PORT1_VECTOR #define CC2420_IRQ_VECTOR PORT1_VECTOR
/* Pin status. */ /* Pin status. */
@ -208,33 +204,69 @@ typedef unsigned long off_t;
#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN))) #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
/* The CC2420 reset pin. */ /* The CC2420 reset pin. */
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN)) #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN)) #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
/* CC2420 voltage regulator enable pin. */ /* CC2420 voltage regulator enable pin. */
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN)) #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN)) #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */ /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
#define CC2420_FIFOP_INT_INIT() do { \ #define CC2420_FIFOP_INT_INIT() do { \
CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \ CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
CC2420_CLEAR_FIFOP_INT(); \ CC2420_CLEAR_FIFOP_INT(); \
} while(0) } while(0)
/* FIFOP on external interrupt 0. */ /* FIFOP on external interrupt 0. */
#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0) #define CC2420_ENABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN); } while(0)
#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0) #define CC2420_DISABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN); } while(0)
#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0) #define CC2420_CLEAR_FIFOP_INT() do { CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN); } while(0)
/* /*
* Enables/disables CC2420 access to the SPI bus (not the bus). * Enables/disables CC2420 access to the SPI bus (not the bus).
* (Chip Select) * (Chip Select)
*/ */
/* ENABLE CSn (active low) */ /* ENABLE CSn (active low) */
#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN)) #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
/* DISABLE CSn (active low) */ /* DISABLE CSn (active low) */
#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN)) #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN)) #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
/*
* I2C configuration
*/
#define I2C_PxDIR P5DIR
#define I2C_PxIN P5IN
#define I2C_PxOUT P5OUT
#define I2C_PxSEL P5SEL
#define I2C_PxSEL2 P5SEL2
#define I2C_PxREN P5REN
#define I2C_SDA (1 << 1) /* SDA == P5.1 */
#define I2C_SCL (1 << 2) /* SCL == P5.2 */
#define I2C_PRESC_1KHZ_LSB 0x00
#define I2C_PRESC_1KHZ_MSB 0x20
#define I2C_PRESC_100KHZ_LSB 0x50
#define I2C_PRESC_100KHZ_MSB 0x00
#define I2C_PRESC_400KHZ_LSB 0x14
#define I2C_PRESC_400KHZ_MSB 0x00
/* Set rate as high as possible by default */
#ifndef I2C_PRESC_Z1_LSB
#define I2C_PRESC_Z1_LSB I2C_PRESC_400KHZ_LSB
#endif
#ifndef I2C_PRESC_Z1_MSB
#define I2C_PRESC_Z1_MSB I2C_PRESC_400KHZ_MSB
#endif
/* I2C configuration with RX interrupts */
#ifdef I2C_CONF_RX_WITH_INTERRUPT
#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT
#else /* I2C_CONF_RX_WITH_INTERRUPT */
#define I2C_RX_WITH_INTERRUPT 1
#endif /* I2C_CONF_RX_WITH_INTERRUPT */
#endif /* PLATFORM_CONF_H_ */ #endif /* PLATFORM_CONF_H_ */