Uncrustify.
This commit is contained in:
parent
f576489c6e
commit
096ff72bd9
91
main.c
91
main.c
|
@ -5,57 +5,56 @@ volatile unsigned char ticks = 0;
|
||||||
volatile unsigned char flag_1hz = 0;
|
volatile unsigned char flag_1hz = 0;
|
||||||
|
|
||||||
__attribute__((interrupt))
|
__attribute__((interrupt))
|
||||||
void wdti_handler(void)
|
void
|
||||||
|
wdti_handler(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((interrupt))
|
__attribute__((interrupt))
|
||||||
void it_handler(void)
|
void
|
||||||
|
it_handler(void)
|
||||||
{
|
{
|
||||||
++ticks;
|
++ticks;
|
||||||
LED1 ^= 1;
|
LED1 ^= 1;
|
||||||
if (0 == (0x07 & ticks))
|
if(0 == (0x07 & ticks)) {
|
||||||
{
|
flag_1hz = 1;
|
||||||
flag_1hz = 1;
|
}
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
int
|
||||||
int main(void)
|
main(void)
|
||||||
{
|
{
|
||||||
asm("di");
|
asm ("di");
|
||||||
/* Setup LEDs */
|
/* Setup LEDs */
|
||||||
LED1 = 1;
|
LED1 = 1;
|
||||||
LED2 = 1;
|
LED2 = 1;
|
||||||
LED1_PIN = 0;
|
LED1_PIN = 0;
|
||||||
LED2_PIN = 0;
|
LED2_PIN = 0;
|
||||||
/* Setup clocks */
|
/* Setup clocks */
|
||||||
CMC.cmc = 0x11U; /* Enable XT1, disable X1 */
|
CMC.cmc = 0x11U; /* Enable XT1, disable X1 */
|
||||||
CSC.csc = 0x80U; /* Start XT1 and HOCO, stop X1 */
|
CSC.csc = 0x80U; /* Start XT1 and HOCO, stop X1 */
|
||||||
CKC.ckc = 0x00U;
|
CKC.ckc = 0x00U;
|
||||||
/* Delay 1 second */
|
/* Delay 1 second */
|
||||||
register unsigned long int i;
|
register unsigned long int i;
|
||||||
for (i = 0x000FFFFFUL; i; --i)
|
for(i = 0x000FFFFFUL; i; --i) {
|
||||||
asm("nop");
|
asm ("nop");
|
||||||
OSMC.osmc = 0x00; /* Supply fsub to peripherals, including Interval Timer */
|
}
|
||||||
uart0_init();
|
OSMC.osmc = 0x00; /* Supply fsub to peripherals, including Interval Timer */
|
||||||
/* Setup 12-bit interval timer */
|
uart0_init();
|
||||||
RTCEN = 1; /* Enable 12-bit interval timer and RTC */
|
/* Setup 12-bit interval timer */
|
||||||
ITMK = 1; /* Disable IT interrupt */
|
RTCEN = 1; /* Enable 12-bit interval timer and RTC */
|
||||||
ITPR0 = 0; /* Set interrupt priority - highest */
|
ITMK = 1; /* Disable IT interrupt */
|
||||||
ITPR1 = 0;
|
ITPR0 = 0; /* Set interrupt priority - highest */
|
||||||
ITMC.itmc = 0x8FFFU; /* Set maximum period 4096/32768Hz = 1/8 s, and start timer */
|
ITPR1 = 0;
|
||||||
ITIF = 0; /* Clear interrupt request flag */
|
ITMC.itmc = 0x8FFFU; /* Set maximum period 4096/32768Hz = 1/8 s, and start timer */
|
||||||
ITMK = 0; /* Enable IT interrupt */
|
ITIF = 0; /* Clear interrupt request flag */
|
||||||
asm ("ei"); /* Enable interrupts */
|
ITMK = 0; /* Enable IT interrupt */
|
||||||
for(;;)
|
asm ("ei"); /* Enable interrupts */
|
||||||
{
|
for(;;) {
|
||||||
if (flag_1hz)
|
if(flag_1hz) {
|
||||||
{
|
LED2 = 0;
|
||||||
LED2 = 0;
|
flag_1hz = 0;
|
||||||
flag_1hz = 0;
|
uart0_puts("Hello, RL78! [:");
|
||||||
uart0_puts("Hello, RL78! [:");
|
LED2 = 1;
|
||||||
LED2 = 1;
|
|
||||||
}
|
|
||||||
asm("halt");
|
|
||||||
}
|
}
|
||||||
|
asm ("halt");
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
142
uart0.c
142
uart0.c
|
@ -2,115 +2,115 @@
|
||||||
#include <iodefine.h>
|
#include <iodefine.h>
|
||||||
#include <iodefine_ext.h>
|
#include <iodefine_ext.h>
|
||||||
|
|
||||||
void uart0_init(void)
|
void
|
||||||
|
uart0_init(void)
|
||||||
{
|
{
|
||||||
/* Reference R01AN0459EJ0100 or hardware manual for details */
|
/* Reference R01AN0459EJ0100 or hardware manual for details */
|
||||||
PIOR.pior = 0U; /* Disable IO redirection */
|
PIOR.pior = 0U; /* Disable IO redirection */
|
||||||
PM1.pm1 |= 0x06U; /* Set P11 and P12 as inputs */
|
PM1.pm1 |= 0x06U; /* Set P11 and P12 as inputs */
|
||||||
SAU0EN = 1; /* Supply clock to serial array unit 0 */
|
SAU0EN = 1; /* Supply clock to serial array unit 0 */
|
||||||
SPS0.sps0 = 0x44U; /* Set input clock (CK00 and CK01) to fclk/16 = 2MHz */
|
SPS0.sps0 = 0x44U; /* Set input clock (CK00 and CK01) to fclk/16 = 2MHz */
|
||||||
ST0.st0 = 0x03U; /* Stop operation of channel 0 and 1 */
|
ST0.st0 = 0x03U; /* Stop operation of channel 0 and 1 */
|
||||||
/* Setup interrupts (disable) */
|
/* Setup interrupts (disable) */
|
||||||
STMK0 = 1; /* Disable INTST0 interrupt */
|
STMK0 = 1; /* Disable INTST0 interrupt */
|
||||||
STIF0 = 0; /* Clear INTST0 interrupt request flag */
|
STIF0 = 0; /* Clear INTST0 interrupt request flag */
|
||||||
STPR10 = 1; /* Set INTST0 priority: lowest */
|
STPR10 = 1; /* Set INTST0 priority: lowest */
|
||||||
STPR00 = 1;
|
STPR00 = 1;
|
||||||
SRMK0 = 1; /* Disable INTSR0 interrupt */
|
SRMK0 = 1; /* Disable INTSR0 interrupt */
|
||||||
SRIF0 = 0; /* Clear INTSR0 interrupt request flag */
|
SRIF0 = 0; /* Clear INTSR0 interrupt request flag */
|
||||||
SRPR10 = 1; /* Set INTSR0 priority: lowest */
|
SRPR10 = 1; /* Set INTSR0 priority: lowest */
|
||||||
SRPR00 = 1;
|
SRPR00 = 1;
|
||||||
SREMK0 = 1; /* Disable INTSRE0 interrupt */
|
SREMK0 = 1; /* Disable INTSRE0 interrupt */
|
||||||
SREIF0 = 0; /* Clear INTSRE0 interrupt request flag */
|
SREIF0 = 0; /* Clear INTSRE0 interrupt request flag */
|
||||||
SREPR10 = 1; /* Set INTSRE0 priority: lowest */
|
SREPR10 = 1; /* Set INTSRE0 priority: lowest */
|
||||||
SREPR00 = 1;
|
SREPR00 = 1;
|
||||||
/* Setup operation mode for transmitter (channel 0) */
|
/* Setup operation mode for transmitter (channel 0) */
|
||||||
SMR00.smr00 = 0x0023U; /* Operation clock : CK00,
|
SMR00.smr00 = 0x0023U; /* Operation clock : CK00,
|
||||||
Transfer clock : division of CK00
|
Transfer clock : division of CK00
|
||||||
Start trigger : software
|
Start trigger : software
|
||||||
Detect falling edge as start bit
|
Detect falling edge as start bit
|
||||||
Operation mode : UART
|
Operation mode : UART
|
||||||
Interrupt source : buffer empty
|
Interrupt source : buffer empty
|
||||||
*/
|
*/
|
||||||
SCR00.scr00 = 0x8097U; /* Transmission only
|
SCR00.scr00 = 0x8097U; /* Transmission only
|
||||||
Reception error interrupt masked
|
Reception error interrupt masked
|
||||||
Phase clock : type 1
|
Phase clock : type 1
|
||||||
No parity
|
No parity
|
||||||
LSB first
|
LSB first
|
||||||
1 stop bit
|
1 stop bit
|
||||||
8-bit data length
|
8-bit data length
|
||||||
*/
|
*/
|
||||||
SDR00.sdr00 = 0xCE00U; /* transfer clock : operation clock divided by 208
|
SDR00.sdr00 = 0xCE00U; /* transfer clock : operation clock divided by 208
|
||||||
2 MHz / 208 = ~9600 bps
|
2 MHz / 208 = ~9600 bps
|
||||||
*/
|
*/
|
||||||
/* Setup operation mode for receiver (channel 1) */
|
/* Setup operation mode for receiver (channel 1) */
|
||||||
NFEN0.nfen0 |= 1; /* Enable noise filter on RxD0 pin */
|
NFEN0.nfen0 |= 1; /* Enable noise filter on RxD0 pin */
|
||||||
SIR01.sir01 = 0x0007U; /* Clear error flags */
|
SIR01.sir01 = 0x0007U; /* Clear error flags */
|
||||||
SMR01.smr01 = 0x0122U; /* Operation clock : CK00
|
SMR01.smr01 = 0x0122U; /* Operation clock : CK00
|
||||||
Transfer clock : division of CK00
|
Transfer clock : division of CK00
|
||||||
Start trigger : valid edge on RxD pin
|
Start trigger : valid edge on RxD pin
|
||||||
Detect falling edge as start bit
|
Detect falling edge as start bit
|
||||||
Operation mode : UART
|
Operation mode : UART
|
||||||
Interrupt source : transfer end
|
Interrupt source : transfer end
|
||||||
*/
|
*/
|
||||||
SCR01.scr01 = 0x4097U; /* Reception only
|
SCR01.scr01 = 0x4097U; /* Reception only
|
||||||
Reception error interrupt masked
|
Reception error interrupt masked
|
||||||
Phase clock : type 1
|
Phase clock : type 1
|
||||||
No parity
|
No parity
|
||||||
LSB first
|
LSB first
|
||||||
1 stop bit
|
1 stop bit
|
||||||
8-bit data length
|
8-bit data length
|
||||||
*/
|
*/
|
||||||
SDR01.sdr01 = 0xCE00U; /* transfer clock : operation clock divided by 208
|
SDR01.sdr01 = 0xCE00U; /* transfer clock : operation clock divided by 208
|
||||||
2 MHz / 208 = ~9600 bps
|
2 MHz / 208 = ~9600 bps
|
||||||
*/
|
*/
|
||||||
SO0.so0 |= 1; /* Prepare for use of channel 0 */
|
SO0.so0 |= 1; /* Prepare for use of channel 0 */
|
||||||
SOE0.soe0 |= 1;
|
SOE0.soe0 |= 1;
|
||||||
P1.p1 |= (1 << 2); /* Set TxD0 high */
|
P1.p1 |= (1 << 2); /* Set TxD0 high */
|
||||||
PM1.pm1 &= ~(1 << 2); /* Set output mode for TxD0 */
|
PM1.pm1 &= ~(1 << 2); /* Set output mode for TxD0 */
|
||||||
PM1.pm1 |= (1 << 1); /* Set input mode for RxD0 */
|
PM1.pm1 |= (1 << 1); /* Set input mode for RxD0 */
|
||||||
SS0.ss0 |= 0x03U; /* Enable UART0 operation (both channels) */
|
SS0.ss0 |= 0x03U; /* Enable UART0 operation (both channels) */
|
||||||
STIF0 = 1; /* Set buffer empty interrupt request flag */
|
STIF0 = 1; /* Set buffer empty interrupt request flag */
|
||||||
}
|
}
|
||||||
|
int
|
||||||
int uart0_puts(const char __far * s)
|
uart0_puts(const char __far *s)
|
||||||
{
|
{
|
||||||
int len = 0;
|
int len = 0;
|
||||||
SMR00.smr00 |= 0x0001U; /* Set buffer empty interrupt */
|
SMR00.smr00 |= 0x0001U; /* Set buffer empty interrupt */
|
||||||
while ('\0' != *s)
|
while('\0' != *s) {
|
||||||
{
|
while(0 == STIF0) ;
|
||||||
while (0 == STIF0);
|
|
||||||
STIF0 = 0;
|
|
||||||
SDR00.sdr00 = *s++;
|
|
||||||
++len;
|
|
||||||
}
|
|
||||||
#if 0
|
|
||||||
while (0 == STIF0);
|
|
||||||
STIF0 = 0;
|
STIF0 = 0;
|
||||||
SDR00.sdr00 = '\r';
|
SDR00.sdr00 = *s++;
|
||||||
#endif
|
++len;
|
||||||
while (0 == STIF0);
|
}
|
||||||
STIF0 = 0;
|
|
||||||
SMR00.smr00 &= ~0x0001U;
|
|
||||||
SDR00.sdr00 = '\n';
|
|
||||||
while (0 == STIF0);
|
|
||||||
#if 0
|
#if 0
|
||||||
while (0 != SSR00.BIT.bit6); /* Wait until TSF00 == 0 */
|
while(0 == STIF0) ;
|
||||||
|
STIF0 = 0;
|
||||||
|
SDR00.sdr00 = '\r';
|
||||||
#endif
|
#endif
|
||||||
return len;
|
while(0 == STIF0) ;
|
||||||
|
STIF0 = 0;
|
||||||
|
SMR00.smr00 &= ~0x0001U;
|
||||||
|
SDR00.sdr00 = '\n';
|
||||||
|
while(0 == STIF0) ;
|
||||||
|
#if 0
|
||||||
|
while(0 != SSR00.BIT.bit6) ; /* Wait until TSF00 == 0 */
|
||||||
|
#endif
|
||||||
|
return len;
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((interrupt))
|
__attribute__((interrupt))
|
||||||
void st0_handler(void)
|
void
|
||||||
|
st0_handler(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
__attribute__((interrupt))
|
__attribute__((interrupt))
|
||||||
void sr0_handler(void)
|
void
|
||||||
|
sr0_handler(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
/* This is actually INTSRE0 interrupt handler */
|
/* This is actually INTSRE0 interrupt handler */
|
||||||
__attribute__((interrupt))
|
__attribute__((interrupt))
|
||||||
void tm01h_handler(void)
|
void
|
||||||
|
tm01h_handler(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue