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Initial WiSMote port based on code from Arago Systems.

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This commit is contained in:
Niclas Finne 2011-09-21 20:02:04 +02:00
parent 367c82a5ab
commit 05b10eb9ce
45 changed files with 5641 additions and 23 deletions
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91
cpu/msp430/dev/uart1.c
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@ -33,7 +33,6 @@
* Machine dependent MSP430 UART1 code.
*/
#include <stdlib.h>
#include "contiki.h"
#include "sys/energest.h"
#include "dev/uart1.h"
@ -93,7 +92,11 @@ handle_rxdma_timer(void *ptr)
uint8_t
uart1_active(void)
{
#if CONTIKI_TARGET_WISMOTE
return rx_in_progress | transmitting;
#else
return ((~ UTCTL1) & TXEPT) | rx_in_progress | transmitting;
#endif
}
/*---------------------------------------------------------------------------*/
void
@ -123,16 +126,21 @@ uart1_writeb(unsigned char c)
/* Loop until the transmission buffer is available. */
/*while((IFG2 & UTXIFG1) == 0);*/
TXBUF1 = ringbuf_get(&txbuf);
UCA1TXBUF = ringbuf_get(&txbuf);
}
#else /* TX_WITH_INTERRUPT */
#if CONTIKI_TARGET_WISMOTE
while(!(UCA1IFG & UCTXIFG)); // USCI_A1 TX buffer ready?
UCA1TXBUF = c;
#else
/* Loop until the transmission buffer is available. */
while((IFG2 & UTXIFG1) == 0);
/* Transmit the data. */
TXBUF1 = c;
#endif
#endif /* TX_WITH_INTERRUPT */
}
/*---------------------------------------------------------------------------*/
@ -143,6 +151,35 @@ uart1_writeb(unsigned char c)
void
uart1_init(unsigned long ubr)
{
#if CONTIKI_TARGET_WISMOTE
P4DIR |= BIT5;
P4OUT |= BIT5 ;
P5SEL |= BIT6|BIT7; // P5.6,7 = USCI_A1 TXD/RXD
P4SEL |= BIT7;
P4DIR |= BIT7;
UCA1CTL1 |= UCSWRST; // **Put state machine in reset**
UCA1CTL1 |= UCSSEL_2; // SMCLK
UCA1BR0 = 139;//69; // Baudrate 57600 (see User's Guide)
UCA1BR1 = 0; //
UCA1MCTL |= UCBRS_2 + UCBRF_0; // Modulation UCBRFx=0
UCA1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA1IE |= UCRXIE;
UCA1IFG &= ~UCRXIFG;
//UCA1IFG &= ~UCTXIFG;
// UCA1TCTL1 |= URXSE;
rx_in_progress = 0;
transmitting = 0;
#if TX_WITH_INTERRUPT
ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
UCA1IE |= UCTXIE;
//UCA1IFG &= ~UCTXIFG;
#endif /* TX_WITH_INTERRUPT */
#else
/* RS232 */
P3DIR &= ~0x80; /* Select P37 for input (UART1RX) */
P3DIR |= 0x40; /* Select P36 for output (UART1TX) */
@ -151,7 +188,7 @@ uart1_init(unsigned long ubr)
UCTL1 = SWRST | CHAR; /* 8-bit character, UART mode */
#if 0
U1RCTL &= ~URXEIE; /* even erroneous characters trigger interrupts */
U1RCTL &= ~URXEIE; /* even erroneous characters trigger interrupts */
#endif
UTCTL1 = SSEL1; /* UCLK = MCLK */
@ -235,10 +272,52 @@ uart1_init(unsigned long ubr)
msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
#endif /* RX_WITH_DMA */
#endif
}
/*---------------------------------------------------------------------------*/
#if CONTIKI_TARGET_WISMOTE
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=USCI_A1_VECTOR
__interrupt void
#else
interrupt(USCI_A1_VECTOR)
#endif
uart1_rx_interrupt(void)
{
uint8_t c;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(UCRXIFG & UCA1IFG) {
rx_in_progress = 0;
// Check status register for receive errors.
if(UCA1STAT & UCRXERR) {
c = UCA1RXBUF; // Clear error flags by forcing a dummy read.
} else {
c = UCA1RXBUF;
if(uart1_input_handler != NULL) {
if(uart1_input_handler(c)) {
LPM4_EXIT;
}
}
}
UCA1IFG &= ~UCRXIFG;
}
#if TX_WITH_INTERRUPT
if(UCTXIFG & UCA1IFG) {
if(ringbuf_elements(&txbuf) == 0) {
transmitting = 0;
} else {
UCA1TXBUF = ringbuf_get(&txbuf);
}
UCA1IFG &= ~UCTXIFG;
}
#endif
//UCA1IFG &= 0x00;
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
#else
#if !RX_WITH_DMA
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=UART1RX_VECTOR
@ -277,7 +356,12 @@ uart1_rx_interrupt(void)
#endif /* !RX_WITH_DMA */
/*---------------------------------------------------------------------------*/
#if TX_WITH_INTERRUPT
#ifdef __IAR_SYSTEMS_ICC__
#pragma vector=UART1TX_VECTOR
__interrupt void
#else
interrupt(UART1TX_VECTOR)
#endif
uart1_tx_interrupt(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
@ -291,4 +375,5 @@ uart1_tx_interrupt(void)
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
#endif /* TX_WITH_INTERRUPT */
#endif
/*---------------------------------------------------------------------------*/