general header updates
This commit is contained in:
Mariano Alvira
parent
0678e778b1
commit
0037fd9527
4 changed files with 88 additions and 30 deletions
|
|
@ -46,8 +46,8 @@
|
|||
#define ROSC_FTUNE 4 /* 4 bits */
|
||||
#define ROSC_EN 0
|
||||
|
||||
#define ring_osc_on() (set_bit(reg32(CRM_RINGOSC_CNTL),ROSC_EN))
|
||||
#define ring_osc_off() (clear_bit(reg32(CRM_RINGOSC_CNTL),ROSC_EN))
|
||||
#define ring_osc_on() (set_bit(*CRM_RINGOSC_CNTL,ROSC_EN))
|
||||
#define ring_osc_off() (clear_bit(*CRM_RINGOSC_CNTL,ROSC_EN))
|
||||
|
||||
#define REF_OSC 24000000ULL /* reference osc. frequency */
|
||||
#define NOMINAL_RING_OSC_SEC 2000 /* nominal ring osc. frequency */
|
||||
|
|
@ -57,34 +57,34 @@
|
|||
#define XTAL32_GAIN 4 /* 2 bits */
|
||||
#define XTAL32_EN 0
|
||||
|
||||
#define xtal32_on() (set_bit(reg32(CRM_XTAL32_CNTL),XTAL32_EN))
|
||||
#define xtal32_off() (clear_bit(reg32(CRM_XTAL32_CNTL),XTAL32_EN))
|
||||
#define xtal32_exists() (set_bit(reg32(CRM_SYS_CNTL),XTAL32_EXISTS))
|
||||
#define xtal32_on() (set_bit(*CRM_XTAL32_CNTL,XTAL32_EN))
|
||||
#define xtal32_off() (clear_bit(*CRM_XTAL32_CNTL,XTAL32_EN))
|
||||
#define xtal32_exists() (set_bit(*CRM_SYS_CNTL,XTAL32_EXISTS))
|
||||
|
||||
/* enable external wake-ups on kbi 4-7 */
|
||||
/* see kbi.h for other kbi specific macros */
|
||||
#define enable_ext_wu(kbi) (set_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+kbi-4)))
|
||||
#define disable_ext_wu(kbi) (clear_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+kbi-4)))
|
||||
#define enable_ext_wu(kbi) (set_bit(*CRM_WU_CNTL,(EXT_WU_EN+kbi-4)))
|
||||
#define disable_ext_wu(kbi) (clear_bit(*CRM_WU_CNTL,(EXT_WU_EN+kbi-4)))
|
||||
|
||||
#define is_ext_wu_evt(kbi) (bit_is_set(reg32(CRM_STATUS),(EXT_WU_EVT+kbi-4)))
|
||||
#define clear_ext_wu_evt(kbi) (set_bit(reg32(CRM_STATUS),(EXT_WU_EVT+kbi-4))) /* r1wc bit */
|
||||
#define is_ext_wu_evt(kbi) (bit_is_set(*CRM_STATUS,(EXT_WU_EVT+kbi-4)))
|
||||
#define clear_ext_wu_evt(kbi) (set_bit(*CRM_STATUS,(EXT_WU_EVT+kbi-4))) /* r1wc bit */
|
||||
|
||||
/* enable wake-up timer */
|
||||
#define enable_timer_wu_irq() ((set_bit(reg32(CRM_WU_CNTL),(TIMER_WU_IEN))))
|
||||
#define disable_timer_wu_irq() ((clear_bit(reg32(CRM_WU_CNTL),(TIMER_WU_IEN))))
|
||||
#define enable_timer_wu_irq() ((set_bit(*CRM_WU_CNTL,(TIMER_WU_IEN))))
|
||||
#define disable_timer_wu_irq() ((clear_bit(*CRM_WU_CNTL,(TIMER_WU_IEN))))
|
||||
|
||||
#define enable_timer_wu() ((set_bit(reg32(CRM_WU_CNTL),(TIMER_WU_EN))))
|
||||
#define disable_timer_wu() ((clear_bit(reg32(CRM_WU_CNTL),(TIMER_WU_EN))))
|
||||
#define enable_timer_wu() ((set_bit(*CRM_WU_CNTL,(TIMER_WU_EN))))
|
||||
#define disable_timer_wu() ((clear_bit(*CRM_WU_CNTL,(TIMER_WU_EN))))
|
||||
|
||||
/* enable wake-up from RTC compare */
|
||||
#define enable_rtc_wu_irq() (set_bit(reg32(CRM_WU_CNTL),RTC_WU_IEN))
|
||||
#define disable_rtc_wu_irq() (clear_bit(reg32(CRM_WU_CNTL),RTC_WU_IEN))
|
||||
#define enable_rtc_wu_irq() (set_bit(*CRM_WU_CNTL,RTC_WU_IEN))
|
||||
#define disable_rtc_wu_irq() (clear_bit(*CRM_WU_CNTL,RTC_WU_IEN))
|
||||
|
||||
#define enable_rtc_wu() ((set_bit(reg32(CRM_WU_CNTL),(RTC_WU_EN))))
|
||||
#define disable_rtc_wu() ((clear_bit(reg32(CRM_WU_CNTL),(RTC_WU_EN))))
|
||||
#define enable_rtc_wu() ((set_bit(*CRM_WU_CNTL,(RTC_WU_EN))))
|
||||
#define disable_rtc_wu() ((clear_bit(*CRM_WU_CNTL,(RTC_WU_EN))))
|
||||
|
||||
#define clear_rtc_wu_evt() (set_bit(reg32(CRM_STATUS),RTC_WU_EVT))
|
||||
#define rtc_wu_evt() (bit_is_set(reg32(CRM_STATUS),RTC_WU_EVT))
|
||||
#define clear_rtc_wu_evt() (set_bit(*CRM_STATUS,RTC_WU_EVT))
|
||||
#define rtc_wu_evt() (bit_is_set(*CRM_STATUS,RTC_WU_EVT))
|
||||
|
||||
#define SLEEP_MODE_HIBERNATE bit(0)
|
||||
#define SLEEP_MODE_DOZE bit(1)
|
||||
|
|
|
|||
|
|
@ -1,18 +1,57 @@
|
|||
#ifndef ISR_H
|
||||
#define ISR_H
|
||||
|
||||
#define INTBASE (0x80020000)
|
||||
#define INTENNUM_OFF (0x8)
|
||||
#define INTDISNUM_OFF (0xc)
|
||||
#define INTSRC_OFF (0x30)
|
||||
#define INTBASE (0x80020000)
|
||||
#define INTCNTL_OFF (0x0)
|
||||
#define INTENNUM_OFF (0x8)
|
||||
#define INTDISNUM_OFF (0xC)
|
||||
#define INTENABLE_OFF (0x10)
|
||||
#define INTSRC_OFF (0x30)
|
||||
#define NIPEND_OFF (0x38)
|
||||
|
||||
#define INTENNUM INTBASE + INTENNUM_OFF
|
||||
#define INTDISNUM INTBASE + INTDISNUM_OFF
|
||||
#define INTSRC INTBASE + INTSRC_OFF
|
||||
#define INTCNTL ((volatile uint32_t *) (INTBASE + INTCNTL_OFF))
|
||||
#define INTENNUM ((volatile uint32_t *) (INTBASE + INTENNUM_OFF))
|
||||
#define INTDISNUM ((volatile uint32_t *) (INTBASE + INTDISNUM_OFF))
|
||||
#define INTENABLE ((volatile uint32_t *) (INTBASE + INTENABLE_OFF))
|
||||
#define INTSRC ((volatile uint32_t *) (INTBASE + INTSRC_OFF))
|
||||
#define NIPEND ((volatile uint32_t *) (INTBASE + NIPEND_OFF))
|
||||
|
||||
#define enable_tmr_irq() *(volatile uint32_t *)(INTENNUM) = 5;
|
||||
enum interrupt_nums {
|
||||
INT_NUM_ASM = 0,
|
||||
INT_NUM_UART1,
|
||||
INT_NUM_UART2,
|
||||
INT_NUM_CRM,
|
||||
INT_NUM_I2C,
|
||||
INT_NUM_TMR,
|
||||
INT_NUM_SPIF,
|
||||
INT_NUM_MACA,
|
||||
INT_NUM_SSI,
|
||||
INT_NUM_ADC,
|
||||
INT_NUM_SPI,
|
||||
};
|
||||
|
||||
#define global_irq_disable() (set_bit(*INTCNTL,20))
|
||||
#define global_irq_enable() (clear_bit(*INTCNTL,20))
|
||||
|
||||
#define enable_irq(irq) (*INTENNUM = INT_NUM_##irq)
|
||||
#define disable_irq(irq) (*INTDISNUM = INT_NUM_##irq)
|
||||
|
||||
|
||||
extern void tmr0_isr(void) __attribute__((weak));
|
||||
extern void tmr1_isr(void) __attribute__((weak));
|
||||
extern void tmr2_isr(void) __attribute__((weak));
|
||||
extern void tmr3_isr(void) __attribute__((weak));
|
||||
|
||||
extern void rtc_isr(void) __attribute__((weak));
|
||||
extern void kbi4_isr(void) __attribute__((weak));
|
||||
extern void kbi5_isr(void) __attribute__((weak));
|
||||
extern void kbi6_isr(void) __attribute__((weak));
|
||||
extern void kbi7_isr(void) __attribute__((weak));
|
||||
|
||||
extern void uart1_isr(void) __attribute__((weak));
|
||||
|
||||
extern void maca_isr(void) __attribute__((weak));
|
||||
|
||||
extern void tmr_isr(void) __attribute__((weak));
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
19
lib/include/kbi.h
Normal file
19
lib/include/kbi.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
#ifndef KBI_H
|
||||
#define KBI_H
|
||||
|
||||
#define enable_irq_kbi(k) (set_bit(*CRM_WU_CNTL,(EXT_WU_IEN+k-4)))
|
||||
#define disable_irq_kbi(k) (clear_bit(*CRM_WU_CNTL,(EXT_WU_IEN+k-4)))
|
||||
|
||||
#define kbi_evnt(k) (bit_is_set(*CRM_STATUS,(EXT_WU_EVT+k-4)))
|
||||
|
||||
#define kbi_edge(k) (set_bit(*CRM_WU_CNTL,(EXT_WU_EDGE+k-4)))
|
||||
#define kbi_level(k) (clear_bit(*CRM_WU_CNTL,(EXT_WU_EDGE+k-4)))
|
||||
|
||||
#define kbi_pol_neg(k) (clear_bit(*CRM_WU_CNTL,(EXT_WU_POL+k-4)))
|
||||
#define kbi_pol_pos(k) (set_bit(*CRM_WU_CNTL,(EXT_WU_POL+k-4)))
|
||||
|
||||
/* you have to clear these events by writing a one to them */
|
||||
|
||||
#define clear_kbi_evnt(k) (set_bit(*CRM_STATUS,(EXT_WU_EVT+k-4)))
|
||||
|
||||
#endif
|
||||
|
|
@ -7,10 +7,10 @@
|
|||
#include "crm.h"
|
||||
#include "nvm.h"
|
||||
#include "tmr.h"
|
||||
#include "kbi.h"
|
||||
#include "maca.h"
|
||||
#include "packet.h"
|
||||
#include "uart1.h"
|
||||
#include "utils.h"
|
||||
|
||||
#include "put.h" /* this is a temp. lib */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue