osd-contiki/cpu/x86/init/common/cpu.c

125 lines
4.4 KiB
C
Raw Normal View History

/*
* Copyright (C) 2015, Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu.h"
#include "gdt.h"
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 22:18:27 +02:00
#include "helpers.h"
#include "idt.h"
#include "interrupt.h"
#include "irq.h"
#include "stacks.h"
static void
double_fault_handler(struct interrupt_context context)
{
halt();
}
/*---------------------------------------------------------------------------*/
/* The OS has switched to its own segment descriptors. When multi-segment
* protection domain support is enabled, this routine runs with the
* necessary address translations configured to invoke other routines that
* require those translations to be in place. However, the protection domain
* support, if enabled, has not yet been fully activated.
*/
static void
boot_stage1(void)
{
idt_init();
/* Set an interrupt handler for Double Fault exception. This way, we avoid
* the system to triple fault, leaving no trace about what happened.
*/
SET_EXCEPTION_HANDLER(8, 1, double_fault_handler);
/* Initialize protection domain support, if enabled */
prot_domains_init();
prot_domains_leave_boot_stage1();
}
/*---------------------------------------------------------------------------*/
int main(void);
/* This routine runs with the initial, flat address space, even if protection
* domain support is enabled. The goal behind the design of this routine is to
* keep it as short as possible, since it is unable to directly reference data
* and invoke functions that are intended to be accessible later after the
* system has booted when a multi-segment protection domain model is in use.
*/
void
cpu_boot_stage0(void)
{
/* Reserve three stack slots for return addresses */
uintptr_t top_of_stack = STACKS_INIT_TOP;
#if X86_CONF_PROT_DOMAINS != X86_CONF_PROT_DOMAINS__NONE
uintptr_t *top_of_stack_ptr =
(uintptr_t *)DATA_OFF_TO_PHYS_ADDR(top_of_stack);
top_of_stack_ptr[0] = (uintptr_t)prot_domains_launch_kernel;
top_of_stack_ptr[1] = (uintptr_t)prot_domains_launch_app;
#endif
/* Perform common GDT initialization */
gdt_init();
/* Switch all data segment registers to the newly-initialized flat data
* descriptor.
*/
__asm__(
"mov %0, %%ds\n\t"
"mov %0, %%es\n\t"
"mov %0, %%fs\n\t"
"mov %0, %%gs\n\t"
:
: "r" (GDT_SEL_DATA_FLAT)
);
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 22:18:27 +02:00
/**
* Perform specific GDT initialization tasks for the protection domain
* implementation that is enabled, if any.
*/
prot_domains_gdt_init();
/* Do not pass memory operands to the asm block below, since it is
* switching from the flat address space to a multi-segment address space
* model if such a model is used by the enabled protection domain
* implementation, if any.
*/
__asm__(
"mov %[_ss_], %%ss\n\t"
"mov %[_esp_], %%esp\n\t"
"ljmp %[_cs_], %[_stage1_]\n\t"
:
: [_ss_] "r" (GDT_SEL_STK_EXC),
[_esp_] "r" (top_of_stack),
[_cs_] "i" ((uint16_t)GDT_SEL_CODE_EXC),
[_stage1_] "i" (boot_stage1)
);
}