317 lines
7.5 KiB
C
317 lines
7.5 KiB
C
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/*
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* Copyright (c) 2005, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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* @(#)$Id: msp430.c,v 1.1 2010/08/24 16:26:38 joxe Exp $
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*/
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#include "contiki.h"
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#ifdef __IAR_SYSTEMS_ICC__
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#include <msp430.h>
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#else
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#include <io.h>
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#include <signal.h>
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#endif
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#include "dev/watchdog.h"
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#include "dev/leds.h"
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#include "net/uip.h"
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static unsigned long dco_speed;
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/*---------------------------------------------------------------------------*/
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#if defined(__MSP430__) && defined(__GNUC__) && MSP430_MEMCPY_WORKAROUND
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void *
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w_memcpy(void *out, const void *in, size_t n)
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{
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uint8_t *src, *dest;
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src = (uint8_t *) in;
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dest = (uint8_t *) out;
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while(n-- > 0) {
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*dest++ = *src++;
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}
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return out;
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}
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#endif /* __GNUC__ && __MSP430__ && MSP430_MEMCPY_WORKAROUND */
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/*---------------------------------------------------------------------------*/
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#if defined(__MSP430__) && defined(__GNUC__) && MSP430_MEMCPY_WORKAROUND
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void *
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w_memset(void *out, int value, size_t n)
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{
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uint8_t *dest;
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dest = (uint8_t *) out;
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while(n-- > 0) {
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*dest++ = value & 0xff;
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}
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return out;
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}
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#endif /* __GNUC__ && __MSP430__ && MSP430_MEMCPY_WORKAROUND */
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/*---------------------------------------------------------------------------*/
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void
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msp430_init_dco(void)
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{
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}
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/*---------------------------------------------------------------------------*/
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unsigned long
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msp430_dco_speed(void)
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{
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return dco_speed;
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}
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/*---------------------------------------------------------------------------*/
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void
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msp430_set_dco_speed(unsigned long mhz)
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{
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int multiplier;
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dco_speed = mhz;
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dint();
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/* DCO multiplier m for x MHz:
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(m + 1) * FLLRef = Fdco
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(m + 1) * 32768 = x MHz
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m = x / 32768 - 1
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Set FLL Div = fDCOCLK/2
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*/
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multiplier = mhz / 32768UL - 1;
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__bis_SR_register(SCG0);
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UCSCTL0 = 0x0000;
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/* Select DCO range 24MHz operation */
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UCSCTL1 = DCORSEL_5;
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/* Set computed DCO multiplier */
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UCSCTL2 = FLLD_1 + multiplier;
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__bic_SR_register(SCG0);
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do {
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/* Clear XT2,XT1,DCO fault flags */
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UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
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/* Clear fault flags */
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SFRIFG1 &= ~OFIFG;
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__delay_cycles(10000);
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/* Test oscillator fault flag */
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} while(SFRIFG1 & OFIFG);
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UCSCTL3 |= SELREF_0;
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UCSCTL4 |= SELA_0;
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eint();
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}
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/*---------------------------------------------------------------------------*/
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void
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msp430_quick_synch_dco(void)
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{
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msp430_set_dco_speed(F_CPU);
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}
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/*---------------------------------------------------------------------------*/
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static void
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init_ports(void)
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{
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/* Turn everything off, device drivers enable what is needed. */
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/* All configured for digital I/O */
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#ifdef P1SEL
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P1SEL = 0;
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#endif
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#ifdef P2SEL
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P2SEL = 0;
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#endif
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#ifdef P3SEL
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P3SEL = 0;
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#endif
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#ifdef P4SEL
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P4SEL = 0;
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#endif
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#ifdef P5SEL
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P5SEL = 0;
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#endif
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#ifdef P6SEL
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P6SEL = 0;
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#endif
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/* All available inputs */
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#ifdef P1DIR
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P1DIR = 0;
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P1OUT = 0;
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#endif
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#ifdef P2DIR
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P2DIR = 1 << 6; /* output needed for the below config ? */
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P2OUT = 0;
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P2SEL = 1 << 6; /* test for setting the P2.6 to ACKL output */
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#endif
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#ifdef P3DIR
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P3DIR = 0;
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P3OUT = 0;
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#endif
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#ifdef P4DIR
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P4DIR = 0;
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P4OUT = 0;
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#endif
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#ifdef P5DIR
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P5DIR = 0;
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P5OUT = 0;
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#endif
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#ifdef P6DIR
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P6DIR = 0;
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P6OUT = 0;
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#endif
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#ifdef P7DIR
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P7DIR = 0;
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P7OUT = 0;
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P7SEL |= 0x03; /* Configure for ext clock function on these pins */
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#endif
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#ifdef P8DIR
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P8DIR = 0;
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P8OUT = 0;
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#endif
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P1IE = 0;
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P2IE = 0;
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}
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/*---------------------------------------------------------------------------*/
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/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
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#ifndef __IAR_SYSTEMS_ICC__
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extern int _end; /* Not in sys/unistd.h */
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static char *cur_break = (char *)&_end;
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#endif
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void
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msp430_cpu_init(void)
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{
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dint();
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watchdog_init();
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init_ports();
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dco_speed = 1048576; /* Default bootup DCO frequency */
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msp430_quick_synch_dco();
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eint();
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#ifndef __IAR_SYSTEMS_ICC__
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if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */
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cur_break++;
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}
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#endif
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}
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/*---------------------------------------------------------------------------*/
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#define asmv(arg) __asm__ __volatile__(arg)
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#define STACK_EXTRA 32
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/*
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* Allocate memory from the heap. Check that we don't collide with the
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* stack right now (some other routine might later). A watchdog might
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* be used to check if cur_break and the stack pointer meet during
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* runtime.
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*/
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#if 0
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void *
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sbrk(int incr)
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{
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char *stack_pointer;
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#ifdef __IAR_SYSTEMS_ICC__
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stack_pointer = (char *) __get_SP_register();
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/* TODO: add code here... */
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return 0;
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#else
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asmv("mov r1, %0" : "=r" (stack_pointer));
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stack_pointer -= STACK_EXTRA;
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if(incr > (stack_pointer - cur_break))
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return (void *)-1; /* ENOMEM */
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void *old_break = cur_break;
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cur_break += incr;
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/*
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* If the stack was never here then [old_break .. cur_break] should
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* be filled with zeros.
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*/
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return old_break;
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#endif
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}
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#endif
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/*---------------------------------------------------------------------------*/
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/*
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* Mask all interrupts that can be masked.
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*/
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int
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splhigh_(void)
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{
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/* Clear the GIE (General Interrupt Enable) flag. */
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int sr;
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#ifdef __IAR_SYSTEMS_ICC__
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sr = __get_SR_register();
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__bic_SR_register(GIE);
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#else
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asmv("mov r2, %0" : "=r" (sr));
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asmv("bic %0, r2" : : "i" (GIE));
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#endif
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return sr & GIE; /* Ignore other sr bits. */
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}
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/*---------------------------------------------------------------------------*/
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/*
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* Restore previous interrupt mask.
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*/
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void
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splx_(int sr)
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{
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/* If GIE was set, restore it. */
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#ifdef __IAR_SYSTEMS_ICC__
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__bis_SR_register(sr);
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#else
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asmv("bis %0, r2" : : "r" (sr));
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#endif
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}
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#ifdef __IAR_SYSTEMS_ICC__
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int __low_level_init(void)
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{
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/* turn off watchdog so that C-init will run */
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WDTCTL = WDTPW + WDTHOLD;
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/*
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* Return value:
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*
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* 1 - Perform data segment initialization.
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* 0 - Skip data segment initialization.
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*/
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return 1;
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}
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#endif
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/*---------------------------------------------------------------------------*/
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void
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msp430_sync_dco(void)
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{
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}
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/*---------------------------------------------------------------------------*/
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