2014-10-07 00:07:22 +02:00
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_Core_FunctionInterface
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_core_register
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_glob_defs
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_MISRA_Exceptions
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_core_definitions
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_SIMD_intrinsics
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \addtogroup CMSIS_Core_InstructionInterface
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \defgroup Cortex_M0 Cortex-M0
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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2016-07-14 00:20:59 +02:00
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/**
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* \defgroup Cortex-M0+ Cortex-M0+
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* \ingroup cmsis
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*/
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2014-10-07 00:07:22 +02:00
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/**
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2016-07-17 21:50:42 +02:00
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* \defgroup Cortex_M3 Cortex-M3
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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/**
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2016-07-17 21:50:42 +02:00
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* \defgroup Cortex_M4 Cortex-M4
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* \ingroup cmsis
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2014-10-07 00:07:22 +02:00
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*/
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2016-07-14 00:20:59 +02:00
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/**
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* \defgroup Cortex_M7 Cortex-M7
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* \ingroup cmsis
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*/
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