145 lines
5.7 KiB
C
145 lines
5.7 KiB
C
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/*
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* Template:
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* Copyright (c) 2012 ARM LIMITED
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* All rights reserved.
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*
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* CC2538:
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* Copyright (c) 2016, Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-cm3 CC2538 Cortex-M3
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*
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* CC2538 Cortex-M3 CMSIS definitions
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* @{
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*
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* \file
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* CMSIS Cortex-M3 core peripheral access layer header file for CC2538
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*/
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#ifndef CC2538_CM3_H
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#define CC2538_CM3_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup CC2538_CMSIS CC2538 CMSIS Definitions
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* Configuration of the Cortex-M3 Processor and Core Peripherals
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* @{
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*/
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/** \name Interrupt Number Definition
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* @{
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*/
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ****************************/
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
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/****** CC2538-Specific Interrupt Numbers *********************************/
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GPIO_A_IRQn = 0, /**< GPIO port A Interrupt */
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GPIO_B_IRQn = 1, /**< GPIO port B Interrupt */
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GPIO_C_IRQn = 2, /**< GPIO port C Interrupt */
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GPIO_D_IRQn = 3, /**< GPIO port D Interrupt */
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UART0_IRQn = 5, /**< UART0 Interrupt */
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UART1_IRQn = 6, /**< UART1 Interrupt */
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SSI0_IRQn = 7, /**< SSI0 Interrupt */
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I2C_IRQn = 8, /**< I²C Interrupt */
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ADC_IRQn = 14, /**< ADC Interrupt */
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WDT_IRQn = 18, /**< Watchdog Timer Interrupt */
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GPT0A_IRQn = 19, /**< GPTimer 0A Interrupt */
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GPT0B_IRQn = 20, /**< GPTimer 0B Interrupt */
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GPT1A_IRQn = 21, /**< GPTimer 1A Interrupt */
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GPT1B_IRQn = 22, /**< GPTimer 1B Interrupt */
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GPT2A_IRQn = 23, /**< GPTimer 2A Interrupt */
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GPT2B_IRQn = 24, /**< GPTimer 2B Interrupt */
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ADC_CMP_IRQn = 25, /**< Analog Comparator Interrupt */
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RF_TX_RX_ALT_IRQn = 26, /**< RF Tx/Rx (Alternate) Interrupt */
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RF_ERR_ALT_IRQn = 27, /**< RF Error (Alternate) Interrupt */
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SYS_CTRL_IRQn = 28, /**< System Control Interrupt */
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FLASH_CTRL_IRQn = 29, /**< Flash memory Control Interrupt */
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AES_ALT_IRQn = 30, /**< AES (Alternate) Interrupt */
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PKA_ALT_IRQn = 31, /**< PKA (Alternate) Interrupt */
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SMT_ALT_IRQn = 32, /**< SM Timer (Alternate) Interrupt */
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MACT_ALT_IRQn = 33, /**< MAC Timer (Alternate) Interrupt */
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SSI1_IRQn = 34, /**< SSI1 Interrupt */
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GPT3A_IRQn = 35, /**< GPTimer 3A Interrupt */
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GPT3B_IRQn = 36, /**< GPTimer 3B Interrupt */
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UDMA_SW_IRQn = 46, /**< µDMA Software Interrupt */
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UDMA_ERR_IRQn = 47, /**< µDMA Error Interrupt */
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USB_IRQn = 140, /**< USB Interrupt */
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RF_TX_RX_IRQn = 141, /**< RF Tx/Rx Interrupt */
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RF_ERR_IRQn = 142, /**< RF Error Interrupt */
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AES_IRQn = 143, /**< AES Interrupt */
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PKA_IRQn = 144, /**< PKA Interrupt */
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SMT_IRQn = 145, /**< SM Timer Interrupt */
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MACT_IRQn = 146 /**< MAC Timer Interrupt */
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} IRQn_Type;
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/** @} */
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/** \name Processor and Core Peripheral Section
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* @{
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __CM3_REV 0x0200 /**< Core Revision r2p0 */
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#define __MPU_PRESENT 1 /**< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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/** @} */
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/** @} */ /* CC2538_CMSIS */
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#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CC2538_CM3_H */
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/**
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* @}
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* @}
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*/
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