deac/osd-contiki
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity
osd-contiki/cpu/x86/init/common/cpu.c

125 lines
4.4 KiB
C
Raw Normal View History

x86: CPU Initialization This patch defines the cpu_init() function which should encapsulate all code related to x86 CPU initialization. For now, this function initializes GDT and IDT.
2015-07-01 23:30:46 +02:00
/*
* Copyright (C) 2015, Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
#include "cpu.h"
x86: CPU Initialization This patch defines the cpu_init() function which should encapsulate all code related to x86 CPU initialization. For now, this function initializes GDT and IDT.
2015-07-01 23:30:46 +02:00
#include "gdt.h"
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 22:18:27 +02:00
#include "helpers.h"
x86: CPU Initialization This patch defines the cpu_init() function which should encapsulate all code related to x86 CPU initialization. For now, this function initializes GDT and IDT.
2015-07-01 23:30:46 +02:00
#include "idt.h"
x86: Set interrupt handler for Double Fault exception This patch sets an interrupt handler for Double Fault exception during CPU initialization. In case such exception is raised, we halt the system. This way, we avoid the system to triple fault (due to an unhandled interrupt for instance), leaving no trace about what cause the triple fault.
2015-04-15 22:44:38 +02:00
#include "interrupt.h"
x86: Isolate SoC specific cpu_init code This commit turns cpu_init() into a SoC-agnostic function by removing any SoC specific calls and isolating them into their own SoC implementation. We start this by isolating all IRQs initialization code from the legacy-pc target, pic_init() and spurious IRQ7 registration, into a new interface: irq_init() from irq.h. Future SoCs will have to provide their own implementation of this interface. This model is to be followed by future initialization code that we may need to add and which is not common to all x86 SoCs.
2015-05-08 14:34:32 +02:00
#include "irq.h"
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
#include "stacks.h"
x86: Add a fake IRQ7 handler to avoid spurious interrupts The 8259a PIC has a well known problem of generating flaky IRQ7 interrupts. The correct solution is to always check if an IRQ7 interrupt is real or not by probing the PIC's ISR register. This check is only mandatory if the IRQ7 is actually being used by the system. More importantly, the handler should NEVER send and EOI if the interrupt was spurious. This patch addresses this issue by implementing a fake empty handler for this IRQ and, as stated, NOT sending the EOI.
2015-07-02 23:28:44 +02:00
x86: Set interrupt handler for Double Fault exception This patch sets an interrupt handler for Double Fault exception during CPU initialization. In case such exception is raised, we halt the system. This way, we avoid the system to triple fault (due to an unhandled interrupt for instance), leaving no trace about what cause the triple fault.
2015-04-15 22:44:38 +02:00
static void
double_fault_handler(struct interrupt_context context)
{
halt();
}
/*---------------------------------------------------------------------------*/
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2015-08-08 00:43:10 +02:00
/* The OS has switched to its own segment descriptors. When multi-segment
* protection domain support is enabled, this routine runs with the
* necessary address translations configured to invoke other routines that
* require those translations to be in place. However, the protection domain
* support, if enabled, has not yet been fully activated.
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
*/
static void
boot_stage1(void)
x86: CPU Initialization This patch defines the cpu_init() function which should encapsulate all code related to x86 CPU initialization. For now, this function initializes GDT and IDT.
2015-07-01 23:30:46 +02:00
{
idt_init();
x86: Set interrupt handler for Double Fault exception This patch sets an interrupt handler for Double Fault exception during CPU initialization. In case such exception is raised, we halt the system. This way, we avoid the system to triple fault (due to an unhandled interrupt for instance), leaving no trace about what cause the triple fault.
2015-04-15 22:44:38 +02:00
/* Set an interrupt handler for Double Fault exception. This way, we avoid
* the system to triple fault, leaving no trace about what happened.
*/
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
SET_EXCEPTION_HANDLER(8, 1, double_fault_handler);
/* Initialize protection domain support, if enabled */
prot_domains_init();
prot_domains_leave_boot_stage1();
}
/*---------------------------------------------------------------------------*/
int main(void);
/* This routine runs with the initial, flat address space, even if protection
* domain support is enabled. The goal behind the design of this routine is to
* keep it as short as possible, since it is unable to directly reference data
* and invoke functions that are intended to be accessible later after the
* system has booted when a multi-segment protection domain model is in use.
*/
void
cpu_boot_stage0(void)
{
/* Reserve three stack slots for return addresses */
uintptr_t top_of_stack = STACKS_INIT_TOP;
#if X86_CONF_PROT_DOMAINS != X86_CONF_PROT_DOMAINS__NONE
x86: Add TSS-based protection domain support This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
2015-08-08 00:43:10 +02:00
uintptr_t *top_of_stack_ptr =
(uintptr_t *)DATA_OFF_TO_PHYS_ADDR(top_of_stack);
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
top_of_stack_ptr[0] = (uintptr_t)prot_domains_launch_kernel;
top_of_stack_ptr[1] = (uintptr_t)prot_domains_launch_app;
#endif
/* Perform common GDT initialization */
gdt_init();
/* Switch all data segment registers to the newly-initialized flat data
* descriptor.
*/
__asm__(
"mov %0, %%ds\n\t"
"mov %0, %%es\n\t"
"mov %0, %%fs\n\t"
"mov %0, %%gs\n\t"
:
: "r" (GDT_SEL_DATA_FLAT)
);
x86: Initialize the 8259 PIC The Programmable Interrupt Controller is a chip responsible for translating hardware interrupts to system interrupts. When it receives an Interrupt Request (IRQ), it triggers the appropriate interrupt line reaching the appropriate IDT gate, following a previously setup offset. There are 2 daisy-chained PICs. PIC1 handles IRQs 0-7 and PIC2 handles IRQs 8-15. If no vector offset is set, an IRQ0, for instance, would trigger the interrupt 0, clashing with the "Division by zero exception" handler. Thus the IRQs must be remapped. This patch implements the PICs initialization through their 4 Initialization Command Words (ICWs) in a very "canonical" way: - ICW1: the initializing command; - ICW2: the vector offset for the PIC1 and PIC2 (we add an offset of 32 positions); - ICW3: the inter-PICs wiring setup (we connect PIC2 to PIC1's IRQ2); - ICW4: extra systems information (we set PIC1 as Master and PIC2 as slave). It then masks the Interrupt Mask Register, blocking all IRQs but #2 initially. These must be unmasked on demand. The IMR is 8-bits long, so setting the n^th bit to 1 would DISABLE the IRQ n while setting it to 0 would ENABLE IRQ n. As stated, this is an implementation of the legacy 8259 PIC. More investigation is needed so we decide if it is enough or if we need the (newer) APIC implementation instead. This patch also adds the outb() helper function to helpers.h. The helpers is a wrapper for assembly 'out' instruction. Finally, since we now properly support hardware interrupts, this patch also enables IRQs in platform main(). More information: - Quark X1000 Datasheet, section 21.12, page 898. - http://wiki.osdev.org/8259_PIC - http://stanislavs.org/helppc/8259.html
2015-04-08 22:18:27 +02:00
x86: Add support for (paging-based) protection domains This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
2015-08-10 17:34:02 +02:00
/**
* Perform specific GDT initialization tasks for the protection domain
* implementation that is enabled, if any.
*/
prot_domains_gdt_init();
/* Do not pass memory operands to the asm block below, since it is
* switching from the flat address space to a multi-segment address space
* model if such a model is used by the enabled protection domain
* implementation, if any.
*/
__asm__(
"mov %[_ss_], %%ss\n\t"
"mov %[_esp_], %%esp\n\t"
"ljmp %[_cs_], %[_stage1_]\n\t"
:
: [_ss_] "r" (GDT_SEL_STK_EXC),
[_esp_] "r" (top_of_stack),
[_cs_] "i" ((uint16_t)GDT_SEL_CODE_EXC),
[_stage1_] "i" (boot_stage1)
);
x86: CPU Initialization This patch defines the cpu_init() function which should encapsulate all code related to x86 CPU initialization. For now, this function initializes GDT and IDT.
2015-07-01 23:30:46 +02:00
}
Reference in a new issue Copy permalink