2009-05-11 21:52:30 +02:00
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#define GPIO_PAD_DIR0 0x80000000
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#define GPIO_DATA0 0x80000008
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2009-05-11 23:01:31 +02:00
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2009-05-12 23:19:57 +02:00
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#define GPIO_FUNC_SEL0 0x80000018 /* GPIO 15 - 0; 2 bit blocks */
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2009-05-11 21:52:30 +02:00
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#define GPIO_PAD_PU_EN0 0x80000010
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#define GPIO_PAD_PU_EN1 0x80000014
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#define ADC_CONTROL 0x80000018
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2009-05-11 23:01:31 +02:00
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#define CRM_WU_CNTL 0x80003004
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#define CRM_WU_TIMEOUT 0x80003024
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#define CRM_SLEEP_CNTL 0x80003008
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#define CRM_STATUS 0x80003018
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2009-05-11 21:52:30 +02:00
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#define CRM_XTAL_CNTL 0x80000040
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2009-05-12 23:19:57 +02:00
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#define BASE_UART1 0x80005000
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#define UART1_CON 0x80005000
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#define UART1_STAT 0x80005004
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#define UART1_DATA 0x80005008
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#define UR1CON 0x8000500c
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#define UT1CON 0x80005010
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#define UART1_CTS 0x80005014
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#define UART1_BR 0x80005018
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2009-05-11 21:52:30 +02:00
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#define DELAY 400000
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#include "embedded_types.h"
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#include "isr.h"
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#include "utils.h"
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2009-05-12 23:19:57 +02:00
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#include "maca.h"
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void putc(uint8_t c);
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void puts(uint8_t *s);
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void put_hex(uint8_t x);
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void put_hex16(uint16_t x);
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void put_hex32(uint32_t x);
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const uint8_t hex[16]={'0','1','2','3','4','5','6','7',
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'8','9','a','b','c','d','e','f'};
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typedef void (*pfCallback_t)(void);
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typedef struct
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{
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uint8_t sleepType:1;// 0 hibernate / 1 doze
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uint8_t ramRet:2;
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uint8_t mcuRet:1;
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uint8_t digPadRet:1;
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pfCallback_t pfToDoBeforeSleep;
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}crmSleepCtrl_t;
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void do_nothing(void) {
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return;
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}
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void (*crm_gotosleep)(crmSleepCtrl_t *foo) = 0x0000364d;
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2009-05-11 21:52:30 +02:00
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__attribute__ ((section ("startup"))) void main(void) {
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2009-05-12 23:19:57 +02:00
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crmSleepCtrl_t crmSleepCtrl;
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2009-05-11 21:52:30 +02:00
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reg32(GPIO_PAD_DIR0) = 0x00000100;
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reg32(GPIO_DATA0) = 0x00000100;
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2009-05-12 23:19:57 +02:00
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/* Restore UART regs. to default */
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/* in case there is still bootloader state leftover */
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*(volatile uint32_t *)UART1_CON = 0x0000c800; /* mask interrupts, 16 bit sample --- helps explain the baud rate */
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/* INC = 767; MOD = 9999 works: 115200 @ 24 MHz 16 bit sample */
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#define INC 767
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#define MOD 9999
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*(volatile uint32_t *)UART1_BR = INC<<16 | MOD;
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/* see Section 11.5.1.2 Alternate Modes */
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/* you must enable the peripheral first BEFORE setting the function in GPIO_FUNC_SEL */
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/* From the datasheet: "The peripheral function will control operation of the pad IF */
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/* THE PERIPHERAL IS ENABLED. */
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*(volatile uint32_t *)UART1_CON = 0x00000003; /* enable receive and transmit */
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*(volatile uint32_t *)GPIO_FUNC_SEL0 = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
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reg32(0x00401ffc) = 0x01234567;
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reg32(0x00407ffc) = 0xdeadbeef;
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reg32(0x0040fffc) = 0xface00ff;
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reg32(0x00410000) = 0xabcd0123;
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puts("sleep test\n\r");
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puts("0x00401ffc: ");
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put_hex32(reg32(0x00401ffc));
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puts("\r\n");
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puts("0x00407ffc: ");
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put_hex32(reg32(0x00407ffc));
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puts("\r\n");
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puts("0x0040fffc: ");
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put_hex32(reg32(0x0040fffc));
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puts("\r\n");
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puts("0x00410000: ");
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put_hex32(reg32(0x00410000));
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puts("\r\n");
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/* radio must be OFF before sleeping */
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/* otherwise MCU will not wake up properly */
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/* this is undocumented behavior */
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radio_off();
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2009-05-11 21:52:30 +02:00
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/* disable all pullups */
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/* seems to make a slight difference (2.0uA vs 1.95uA)*/
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2009-05-11 23:01:31 +02:00
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// reg32(GPIO_PAD_PU_EN0) = 0;
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// reg32(GPIO_PAD_PU_EN1) = 0;
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// reg16(ADC_CONTROL) = 0; /* internal Vref2 */
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2009-05-11 21:52:30 +02:00
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// reg16(CRM_XTAL_CNTL) = 0x052; /* default is 0xf52 */ /* doesn't anything w.r.t. power */
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/* go to sleep */
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2009-05-11 23:01:31 +02:00
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// reg32(CRM_WU_CNTL) = 0; /* don't wake up */
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reg32(CRM_WU_CNTL) = 0x1; /* enable wakeup from wakeup timer */
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2009-05-12 23:19:57 +02:00
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// reg32(CRM_WU_TIMEOUT) = 1875000; /* wake 10 sec later if doze */
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reg32(CRM_WU_TIMEOUT) = 20000; /* wake 10 sec later if hibernate w/2kHz*/
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2009-05-11 21:52:30 +02:00
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// reg32(CRM_SLEEP_CNTL) = 1; /* hibernate, RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 2.0uA */
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// reg32(CRM_SLEEP_CNTL) = 0x41; /* hibernate, RAM page 0 only, retain state, don't power GPIO */ /* approx. 10.0uA */
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// reg32(CRM_SLEEP_CNTL) = 0x51; /* hibernate, RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 11.7uA */
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2009-05-11 23:26:10 +02:00
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// reg32(CRM_SLEEP_CNTL) = 0x61; /* hibernate, RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 13.9uA */
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// reg32(CRM_SLEEP_CNTL) = 0x71; /* hibernate, all RAM pages, retain state, don't power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/
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2009-05-12 23:19:57 +02:00
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reg32(CRM_SLEEP_CNTL) = 0xf1; /* hibernate, all RAM pages, retain state, power GPIO */ /* approx. 16.1uA - possibly with periodic refresh*/
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2009-05-11 21:52:30 +02:00
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// reg32(CRM_SLEEP_CNTL) = 2; /* doze , RAM page 0 only, don't retain state, don't power GPIO */ /* approx. 69.2 uA */
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2009-05-12 23:19:57 +02:00
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// reg32(CRM_SLEEP_CNTL) = 0x42; /* doze , RAM page 0 only, retain state, don't power GPIO */ /* approx. 77.3uA */
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2009-05-11 21:52:30 +02:00
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// reg32(CRM_SLEEP_CNTL) = 0x52; /* doze , RAM page 0&1 only, retain state, don't power GPIO */ /* approx. 78.9uA */
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2009-05-11 23:26:10 +02:00
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// reg32(CRM_SLEEP_CNTL) = 0x62; /* doze , RAM page 0,1,2 only, retain state, don't power GPIO */ /* approx. 81.2uA */
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// reg32(CRM_SLEEP_CNTL) = 0x72; /* doze , all RAM pages, retain state, don't power GPIO */ /* approx. 83.4uA - possibly with periodic refresh*/
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// reg32(CRM_SLEEP_CNTL) = 0xf2; /* doze , all RAM pages, retain state, power GPIO */ /* approx. 82.8uA - possibly with periodic refresh*/
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2009-05-11 23:01:31 +02:00
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2009-05-12 23:19:57 +02:00
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/* crmSleepCtrl.sleepType = 0; */
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/* crmSleepCtrl.ramRet = 3; */
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/* crmSleepCtrl.mcuRet = 1; */
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/* crmSleepCtrl.digPadRet = 1; */
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/* crmSleepCtrl.pfToDoBeforeSleep = do_nothing; */
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/* crm_gotosleep(&crmSleepCtrl); */
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2009-05-11 23:03:20 +02:00
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/* wait for the sleep cycle to complete */
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2009-05-11 23:01:31 +02:00
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while((reg32(CRM_STATUS) & 0x1) == 0) { continue; }
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2009-05-11 23:03:20 +02:00
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and powers down */
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reg32(CRM_STATUS) = 1;
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2009-05-11 21:52:30 +02:00
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2009-05-11 23:01:31 +02:00
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/* asleep */
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2009-05-11 23:03:20 +02:00
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/* wait for the awake cycle to complete */
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2009-05-11 23:01:31 +02:00
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while((reg32(CRM_STATUS) & 0x1) == 0) { continue; }
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2009-05-11 23:03:20 +02:00
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/* write 1 to sleep_sync --- this clears the bit (it's a r1wc bit) and finishes wakeup */
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reg32(CRM_STATUS) = 1;
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2009-05-11 21:52:30 +02:00
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2009-05-12 23:19:57 +02:00
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puts("\n\r\n\r\n\r");
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puts("0x00401ffc: ");
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put_hex32(reg32(0x00401ffc));
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puts("\r\n");
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puts("0x00407ffc: ");
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put_hex32(reg32(0x00407ffc));
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puts("\r\n");
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puts("0x0040fffc: ");
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put_hex32(reg32(0x0040fffc));
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puts("\r\n");
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puts("0x00410000: ");
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put_hex32(reg32(0x00410000));
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puts("\r\n");
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2009-05-11 21:52:30 +02:00
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volatile uint32_t i;
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while(1) {
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reg32(GPIO_DATA0) = 0x00000100;
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for(i=0; i<DELAY; i++) { continue; }
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reg32(GPIO_DATA0) = 0x00000000;
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for(i=0; i<DELAY; i++) { continue; }
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};
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}
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2009-05-12 23:19:57 +02:00
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void putc(uint8_t c) {
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while(reg32(UT1CON)==31); /* wait for there to be room in the buffer */
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reg32(UART1_DATA) = c;
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}
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void puts(uint8_t *s) {
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while(s && *s!=0) {
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putc(*s++);
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}
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}
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void put_hex(uint8_t x)
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{
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putc(hex[x >> 4]);
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putc(hex[x & 15]);
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}
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void put_hex16(uint16_t x)
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{
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put_hex((x >> 8) & 0xFF);
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put_hex((x) & 0xFF);
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}
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void put_hex32(uint32_t x)
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{
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put_hex((x >> 24) & 0xFF);
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put_hex((x >> 16) & 0xFF);
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put_hex((x >> 8) & 0xFF);
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put_hex((x) & 0xFF);
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}
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