356 lines
16 KiB
C
356 lines
16 KiB
C
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/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-usb cc2538 USB controller
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*
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* Driver for the cc2538 USB controller.
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*
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* We use the USB core in cpu/cc253x/usb which is known to work on Linux as
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* well as on OS X.
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* @{
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*
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* \file
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* Header file with declarations for the cc2538 USB registers
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*/
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#ifndef USB_REGS_H_
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#define USB_REGS_H_
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#include "contiki-conf.h"
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB Register Offsets
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* @{
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*/
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#define USB_ADDR 0x40089000 /**< Function address */
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#define USB_POW 0x40089004 /**< Power/Control register */
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#define USB_IIF 0x40089008 /**< IN EPs and EP0 interrupt flags */
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#define USB_OIF 0x40089010 /**< OUT endpoint interrupt flags */
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#define USB_CIF 0x40089018 /**< Common USB interrupt flags */
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#define USB_IIE 0x4008901C /**< IN EPs and EP0 interrupt mask */
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#define USB_OIE 0x40089024 /**< Out EPs interrupt-enable mask */
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#define USB_CIE 0x4008902C /**< Common USB interrupt mask */
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#define USB_FRML 0x40089030 /**< Current frame number (low byte) */
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#define USB_FRMH 0x40089034 /**< Current frame number (high) */
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#define USB_INDEX 0x40089038 /**< Current endpoint index register */
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#define USB_CTRL 0x4008903C /**< USB control register */
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#define USB_MAXI 0x40089040 /**< MAX packet size for IN EPs{1-5} */
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#define USB_CS0_CSIL 0x40089044 /**< EP0 Control and Status or IN EPs
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control and status (low) */
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#define USB_CS0 0x40089044 /**< EP0 Control and Status
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(Alias for USB_CS0_CSIL) */
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#define USB_CSIL 0x40089044 /**< IN EPs control and status (low)
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(Alias for USB_CS0_CSIL) */
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#define USB_CSIH 0x40089048 /**< IN EPs control and status (high) */
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#define USB_MAXO 0x4008904C /**< MAX packet size for OUT EPs */
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#define USB_CSOL 0x40089050 /**< OUT EPs control and status (low) */
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#define USB_CSOH 0x40089054 /**< OUT EPs control and status (high) */
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#define USB_CNT0_CNTL 0x40089058 /**< Number of RX bytes in EP0 FIFO
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or number of bytes in EP{1-5}
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OUT FIFO (low) */
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#define USB_CNT0 0x40089058 /**< Number of RX bytes in EP0 FIFO
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(Alias for USB_CNT0_CNTL) */
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#define USB_CNTL 0x40089058 /**< Number of bytes in EP{1-5}
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OUT FIFO (low)
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(Alias for USB_CNT0_CNTL) */
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#define USB_CNTH 0x4008905C /**< Number of bytes in EP{1-5}
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OUT FIFO (high) */
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#define USB_F0 0x40089080 /**< Endpoint-0 FIFO */
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#define USB_F1 0x40089088 /**< Endpoint-1 FIFO */
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#define USB_F2 0x40089090 /**< Endpoint-2 FIFO */
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#define USB_F3 0x40089098 /**< Endpoint-3 FIFO */
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#define USB_F4 0x400890A0 /**< Endpoint-4 FIFO */
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#define USB_F5 0x400890A8 /**< Endpoint-5 FIFO */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_ADDR Register Bit-Masks
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* @{
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*/
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#define USB_ADDR_UPDATE 0x00000080 /**< 1 while address updating */
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#define USB_ADDR_USBADDR 0x0000007F /**< Device address */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_POW Register Bit-Masks
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* @{
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*/
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#define USB_POW_ISO_WAIT_SOF 0x00000080 /**< 1 until SOF received - ISO only */
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#define USB_POW_RST 0x00000008 /**< 1 During reset signaling */
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#define USB_POW_RESUME 0x00000004 /**< Remote wakeup resume signalling */
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#define USB_POW_SUSPEND 0x00000002 /**< Suspend mode entered */
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#define USB_POW_SUSPEND_EN 0x00000001 /**< Suspend enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_IIF Register Bit-Masks
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* @{
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*/
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#define USB_IIF_INEP5IF 0x00000020 /**< IN EP5 Interrupt flag */
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#define USB_IIF_INEP4IF 0x00000010 /**< IN EP4 Interrupt flag */
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#define USB_IIF_INEP3IF 0x00000008 /**< IN EP3 Interrupt flag */
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#define USB_IIF_INEP2IF 0x00000004 /**< IN EP2 Interrupt flag */
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#define USB_IIF_INEP1IF 0x00000002 /**< IN EP1 Interrupt flag */
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#define USB_IIF_EP0IF 0x00000001 /**< EP0 Interrupt flag */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_OIF Register Bit-Masks
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* @{
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*/
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#define USB_OIF_OUTEP5IF 0x00000020 /**< OUT EP5 Interrupt flag */
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#define USB_OIF_OUTEP4IF 0x00000010 /**< OUT EP4 Interrupt flag */
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#define USB_OIF_OUTEP3IF 0x00000008 /**< OUT EP3 Interrupt flag */
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#define USB_OIF_OUTEP2IF 0x00000004 /**< OUT EP2 Interrupt flag */
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#define USB_OIF_OUTEP1IF 0x00000002 /**< OUT EP1 Interrupt flag */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CIF Register Bit-Masks
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* @{
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*/
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#define USB_CIF_SOFIF 0x00000008 /**< Start-of-frame interrupt flag */
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#define USB_CIF_RSTIF 0x00000004 /**< Reset interrupt flag */
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#define USB_CIF_RESUMEIF 0x00000002 /**< Resume interrupt flag */
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#define USB_CIF_SUSPENDIF 0x00000001 /**< Suspend interrupt flag */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_IIE Register Bit-Masks
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* @{
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*/
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#define USB_IIE_INEP5IE 0x00000020 /**< IN EP5 interrupt enable */
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#define USB_IIE_INEP4IE 0x00000010 /**< IN EP4 interrupt enable */
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#define USB_IIE_INEP3IE 0x00000008 /**< IN EP3 interrupt enable */
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#define USB_IIE_INEP2IE 0x00000004 /**< IN EP2 interrupt enable */
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#define USB_IIE_INEP1IE 0x00000002 /**< IN EP1 interrupt enable */
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#define USB_IIE_EP0IE 0x00000001 /**< EP0 interrupt enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_OIE Register Bit-Masks
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* @{
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*/
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#define USB_OIE_OUTEP5IE 0x00000020 /**< OUT EP5 interrupt enable */
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#define USB_OIE_OUTEP4IE 0x00000010 /**< OUT EP4 interrupt enable */
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#define USB_OIE_OUTEP3IE 0x00000008 /**< OUT EP3 interrupt enable */
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#define USB_OIE_OUTEP2IE 0x00000004 /**< OUT EP2 interrupt enable */
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#define USB_OIE_OUTEP1IE 0x00000002 /**< OUT EP1 interrupt enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CIE Register Bit-Masks
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* @{
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*/
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#define USB_CIE_SOFIE 0x00000008 /**< Start-of-frame interrupt enable */
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#define USB_CIE_RSTIE 0x00000004 /**< Reset interrupt enable */
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#define USB_CIE_RESUMEIE 0x00000002 /**< Resume interrupt enable */
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#define USB_CIE_SUSPENDIE 0x00000001 /**< Suspend interrupt enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_FRML Register Bit-Masks
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* @{
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*/
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#define USB_FRML_FRAME 0x000000FF /**< Low byte of 11-bit frame number */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_FRMH Register Bit-Masks
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* @{
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*/
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#define USB_FRMH_FRAME 0x00000007 /**< 3 MSBs of 11-bit frame number */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_INDEX Register Bit-Masks
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* @{
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*/
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#define USB_INDEX_USBINDEX 0x0000000F /**< Endpoint selected */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CTRL Register Bit-Masks
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* @{
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*/
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#define USB_CTRL_PLL_LOCKED 0x00000080 /**< PLL locked status */
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#define USB_CTRL_PLL_EN 0x00000002 /**< 48-MHz USB PLL enable */
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#define USB_CTRL_USB_EN 0x00000001 /**< USB enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_MAXI Register Bit-Masks
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* @{
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*/
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#define USB_MAXI_USBMAXI 0x000000FF /**< Maximum packet size */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CS0_CSIL Register Bit-Masks
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* @{
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*/
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/** Listed as reserved in the UG, is this right? */
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#define USB_CS0_CLR_SETUP_END 0x00000080
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/** Deassert OUTPKT_RDY bit of this register or reset the data toggle to 0 */
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#define USB_CS0_CSIL_CLR_OUTPKT_RDY_or_CLR_DATA_TOG 0x00000040
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#define USB_CS0_CLR_OUTPKT_RDY 0x00000040
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#define USB_CSIL_CLR_DATA_TOG 0x00000040
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/**
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* Set this bit to 1 to terminate the current transaction or
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* is set when a STALL handshake has been sent
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*/
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#define USB_CS0_CSIL_SEND_STALL_or_SENT_STALL 0x00000020
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#define USB_CS0_SEND_STALL 0x00000020
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#define USB_CSIL_SENT_STALL 0x00000020
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/**
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* Is set if the control transfer ends due to a premature end-of-control
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* transfer or set to 1 to make the USB controller reply with a STALL handshake
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* when receiving IN tokens
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*/
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#define USB_CS0_CSIL_SETUP_END_or_SEND_STALL 0x00000010
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#define USB_CS0_SETUP_END 0x00000010
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#define USB_CSIL_SEND_STALL 0x00000010
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/**
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* Signal the end of a data transfer or set to 1 to flush next packet that
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* is ready to transfer from the IN FIFO
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*/
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#define USB_CS0_CSIL_DATA_END_or_FLUSH_PACKET 0x00000008
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#define USB_CS0_DATA_END 0x00000008
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#define USB_CSIL_FLUSH_PACKET 0x00000008
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/**
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* Set when a STALL handshake is sent or set if an IN token is received when
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* INPKT_RDY = 0, and a zero-length data packet is transmitted in response to
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* the IN token. In bulk/interrupt mode, this bit is set when a NAK is returned
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* in response to an IN token
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*/
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#define USB_CS0_CSIL_SENT_STALL_or_UNDERRUN 0x00000004
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#define USB_CS0_SENT_STALL 0x00000004
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#define USB_CSIL_UNDERRUN 0x00000004
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/**
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* Data packet has been loaded into the EP0 FIFO or at least one packet in the
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* IN FIFO
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*/
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#define USB_CS0_CSIL_INPKT_RDY_or_PKT_PRESENT 0x00000002
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#define USB_CS0_INPKT_RDY 0x00000002
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#define USB_CSIL_PKT_PRESENT 0x00000002
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/** Data packet received or data packet has been loaded into the IN FIFO */
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#define USB_CS0_CSIL_OUTPKT_RDY_or_INPKT_RDY 0x00000001
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#define USB_CS0_OUTPKT_RDY 0x00000001
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#define USB_CSIL_INPKT_RDY 0x00000001
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CSIH Register Bit-Masks
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* @{
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*/
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#define USB_CSIH_AUTISET 0x00000080 /**< Auto-assert INPKT_RDY */
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#define USB_CSIH_ISO 0x00000040 /**< Selects IN endpoint type */
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#define USB_CSIH_FORCE_DATA_TOG 0x00000008 /**< IN EP force data toggle switch */
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#define USB_CSIH_IN_DBL_BUF 0x00000001 /**< Double buffering enable (IN FIFO) */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_MAXO Register Bit-Masks
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* @{
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*/
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#define USB_MAXO_USBMAXO 0x000000FF /**< Maximum packet size */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CSOL Register Bit-Masks
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* @{
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*/
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#define USB_CSOL_CLR_DATA_TOG 0x00000080 /**< Setting resets data toggle to 0 */
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#define USB_CSOL_SENT_STALL 0x00000040 /**< STALL handshake sent */
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#define USB_CSOL_SEND_STALL 0x00000020 /**< Reply with STALL to OUT tokens */
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#define USB_CSOL_FLUSH_PACKET 0x00000010 /**< Flush next packet read from OUT FIFO */
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#define USB_CSOL_DATA_ERROR 0x00000008 /**< CRC or bit-stuff error in RX packet */
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#define USB_CSOL_OVERRUN 0x00000004 /**< OUT packet can not be loaded into OUT FIFO */
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#define USB_CSOL_FIFO_FULL 0x00000002 /**< OUT FIFO full */
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#define USB_CSOL_OUTPKT_RDY 0x00000001 /**< OUT packet read in OUT FIFO */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CSOH Register Bit-Masks
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* @{
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*/
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#define USB_CSOH_AUTOCLEAR 0x00000080 /**< Auto-clear OUTPKT_RDY */
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#define USB_CSOH_ISO 0x00000040 /**< Selects OUT endpoint type */
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#define USB_CSOH_OUT_DBL_BUF 0x00000001 /**< Double buffering enable (OUT FIFO) */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/**
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* \name USB_CNT0_CNTL Register Bit-Masks
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* @{
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*/
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#define USB_CNT0_CNTL_USBCNT0 0x0000003F /**< Number of RX bytes in EP0 FIFO */
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|
#define USB_CNT0_USBCNT0 0x0000003F
|
||
|
|
|
||
|
|
#define USB_CNT0_CNTL_USBCNT_5_0 0x0000003F /**< 6 LSBs of the number of RX
|
||
|
|
bytes in EP1-5 OUT FIFO */
|
||
|
|
#define USB_CNTL_USBCNT_5_0 0x0000003F
|
||
|
|
/** @} */
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/**
|
||
|
|
* \name USB_CNTH Register Bit-Masks
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define USB_CNTH_USBCNT 0x00000007 /**< 3 MSBs of RX byte number */
|
||
|
|
/** @} */
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/**
|
||
|
|
* \name USB_F[0-5] Register Bit-Masks
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define USB_F0_USBF0 0x000000FF /**< Endpoint 0 FIFO mask */
|
||
|
|
#define USB_F1_USBF1 0x000000FF /**< Endpoint 1 FIFO mask */
|
||
|
|
#define USB_F2_USBF2 0x000000FF /**< Endpoint 2 FIFO mask */
|
||
|
|
#define USB_F3_USBF3 0x000000FF /**< Endpoint 3 FIFO mask */
|
||
|
|
#define USB_F4_USBF4 0x000000FF /**< Endpoint 4 FIFO mask */
|
||
|
|
#define USB_F5_USBF5 0x000000FF /**< Endpoint 5 FIFO mask */
|
||
|
|
/** @} */
|
||
|
|
|
||
|
|
#endif /* USB_REGS_H_ */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
* @}
|
||
|
|
*/
|