336 lines
16 KiB
C
336 lines
16 KiB
C
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/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-gptimer cc2538 General-Purpose Timers
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*
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* Driver for the cc2538 General Purpose Timers
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* @{
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*
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* \file
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* Header file for the cc2538 General Purpose Timers
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*/
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#ifndef GPTIMER_H_
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#define GPTIMER_H_
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/*---------------------------------------------------------------------------*/
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/** \name Base addresses for the GPT register instances
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* @{
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*/
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#define GPT_0_BASE 0x40030000 /**< GPTIMER0 */
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#define GPT_1_BASE 0x40031000 /**< GPTIMER1 */
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#define GPT_2_BASE 0x40032000 /**< GPTIMER2 */
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#define GPT_3_BASE 0x40033000 /**< GPTIMER3 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER Register offset declarations
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* @{
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*/
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#define GPTIMER_CFG 0x00000000 /**< GPTM configuration */
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#define GPTIMER_TAMR 0x00000004 /**< GPTM Timer A mode */
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#define GPTIMER_TBMR 0x00000008 /**< GPTM Timer B mode */
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#define GPTIMER_CTL 0x0000000C /**< GPTM control */
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#define GPTIMER_SYNC 0x00000010 /**< GPTM synchronize (0 only) */
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#define GPTIMER_IMR 0x00000018 /**< GPTM interrupt mask */
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#define GPTIMER_RIS 0x0000001C /**< GPTM raw interrupt status */
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#define GPTIMER_MIS 0x00000020 /**< GPTM masked interrupt status */
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#define GPTIMER_ICR 0x00000024 /**< GPTM interrupt clear */
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#define GPTIMER_TAILR 0x00000028 /**< GPTM Timer A interval load */
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#define GPTIMER_TBILR 0x0000002C /**< GPTM Timer B interval load */
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#define GPTIMER_TAMATCHR 0x00000030 /**< GPTM Timer A match */
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#define GPTIMER_TBMATCHR 0x00000034 /**< GPTM Timer B match */
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#define GPTIMER_TAPR 0x00000038 /**< GPTM Timer A prescale */
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#define GPTIMER_TBPR 0x0000003C /**< GPTM Timer B prescale */
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#define GPTIMER_TAPMR 0x00000040 /**< GPTM Timer A prescale match */
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#define GPTIMER_TBPMR 0x00000044 /**< GPTM Timer B prescale match */
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#define GPTIMER_TAR 0x00000048 /**< GPTM Timer A */
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#define GPTIMER_TBR 0x0000004C /**< GPTM Timer B */
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#define GPTIMER_TAV 0x00000050 /**< GPTM Timer A value */
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#define GPTIMER_TBV 0x00000054 /**< GPTM Timer B value */
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#define GPTIMER_RTCPD 0x00000058 /**< GPTM RTC predivide */
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#define GPTIMER_TAPS 0x0000005C /**< GPTM Timer A prescale snapshot */
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#define GPTIMER_TBPS 0x00000060 /**< GPTM Timer B prescale snapshot */
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#define GPTIMER_TAPV 0x00000064 /**< GPTM Timer A prescale value */
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#define GPTIMER_TBPV 0x00000068 /**< GPTM Timer B prescale value */
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#define GPTIMER_PP 0x00000FC0 /**< GPTM peripheral properties */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_CFG register bit masks
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* @{
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*/
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#define GPTIMER_CFG_GPTMCFG 0x00000007 /**< configuration */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TnMR bit values
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* @{
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*/
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#define GPTIMER_TAMR_TAMR_ONE_SHOT 0x00000001
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#define GPTIMER_TAMR_TAMR_PERIODIC 0x00000002
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#define GPTIMER_TAMR_TAMR_CAPTURE 0x00000003
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#define GPTIMER_TBMR_TBMR_ONE_SHOT 0x00000001
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#define GPTIMER_TBMR_TBMR_PERIODIC 0x00000002
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#define GPTIMER_TBMR_TBMR_CAPTURE 0x00000003
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAMR register bit masks
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* @{
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*/
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#define GPTIMER_TAMR_TAPLO 0x00000800 /**< Legacy PWM operation */
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#define GPTIMER_TAMR_TAMRSU 0x00000400 /**< Timer A match register update mode */
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#define GPTIMER_TAMR_TAPWMIE 0x00000200 /**< Timer A PWM interrupt enable */
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#define GPTIMER_TAMR_TAILD 0x00000100 /**< Timer A PWM interval load write */
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#define GPTIMER_TAMR_TASNAPS 0x00000080 /**< Timer A snap-shot mode */
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#define GPTIMER_TAMR_TAWOT 0x00000040 /**< Timer A wait-on-trigger */
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#define GPTIMER_TAMR_TAMIE 0x00000020 /**< Timer A match interrupt enable */
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#define GPTIMER_TAMR_TACDIR 0x00000010 /**< Timer A count direction */
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#define GPTIMER_TAMR_TAAMS 0x00000008 /**< Timer A alternate mode */
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#define GPTIMER_TAMR_TACMR 0x00000004 /**< Timer A capture mode */
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#define GPTIMER_TAMR_TAMR 0x00000003 /**< Timer A mode */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBMR register bit masks
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* @{
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*/
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#define GPTIMER_TBMR_TBPLO 0x00000800 /**< Legacy PWM operation */
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#define GPTIMER_TBMR_TBMRSU 0x00000400 /**< Timer B match register update mode */
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#define GPTIMER_TBMR_TBPWMIE 0x00000200 /**< Timer B PWM interrupt enable */
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#define GPTIMER_TBMR_TBILD 0x00000100 /**< Timer B PWM interval load write */
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#define GPTIMER_TBMR_TBSNAPS 0x00000080 /**< Timer B snap-shot mode */
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#define GPTIMER_TBMR_TBWOT 0x00000040 /**< Timer B wait-on-trigger */
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#define GPTIMER_TBMR_TBMIE 0x00000020 /**< Timer B match interrupt enable */
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#define GPTIMER_TBMR_TBCDIR 0x00000010 /**< Timer B count direction */
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#define GPTIMER_TBMR_TBAMS 0x00000008 /**< Timer B alternate mode */
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#define GPTIMER_TBMR_TBCMR 0x00000004 /**< Timer B capture mode */
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#define GPTIMER_TBMR_TBMR 0x00000003 /**< Timer B mode */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_CTL register bit masks
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* @{
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*/
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#define GPTIMER_CTL_TBPWML 0x00004000 /**< Timer B PWM output level */
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#define GPTIMER_CTL_TBOTE 0x00002000 /**< Timer B output trigger enable */
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#define GPTIMER_CTL_TBEVENT 0x00000C00 /**< Timer B event mode */
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#define GPTIMER_CTL_TBSTALL 0x00000200 /**< Timer B stall enable */
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#define GPTIMER_CTL_TBEN 0x00000100 /**< Timer B enable */
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#define GPTIMER_CTL_TAPWML 0x00000040 /**< Timer A PWM output level */
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#define GPTIMER_CTL_TAOTE 0x00000020 /**< Timer A output trigger enable */
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#define GPTIMER_CTL_RTCEN 0x00000010 /**< RTC enable */
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#define GPTIMER_CTL_TAEVENT 0x0000000C /**< Timer A event mode */
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#define GPTIMER_CTL_TASTALL 0x00000002 /**< Timer A stall enable */
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#define GPTIMER_CTL_TAEN 0x00000001 /**< Timer A enable */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_SYNC register bit masks
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* @{
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*/
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#define GPTIMER_SYNC_SYNC3 0x000000C0 /**< Synchronize GPTM3 */
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#define GPTIMER_SYNC_SYNC2 0x00000030 /**< Synchronize GPTM2 */
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#define GPTIMER_SYNC_SYNC1 0x0000000C /**< Synchronize GPTM1 */
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#define GPTIMER_SYNC_SYNC0 0x00000003 /**< Synchronize GPTM0 */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_IMR register bit masks
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* @{
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*/
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#define GPTIMER_IMR_TBMIM 0x00000800 /**< Timer B match int mask */
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#define GPTIMER_IMR_CBEIM 0x00000400 /**< Timer B capture event int mask */
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#define GPTIMER_IMR_CBMIM 0x00000200 /**< Timer B capture match int mask */
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#define GPTIMER_IMR_TBTOIM 0x00000100 /**< Timer B time-out int mask */
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#define GPTIMER_IMR_TAMIM 0x00000010 /**< Timer A match int mask */
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#define GPTIMER_IMR_RTCIM 0x00000008 /**< RTC int mask */
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#define GPTIMER_IMR_CAEIM 0x00000004 /**< Timer A capture event int mask */
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#define GPTIMER_IMR_CAMIM 0x00000002 /**< Timer A capture match int mask */
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#define GPTIMER_IMR_TATOIM 0x00000001 /**< Timer A time-out int mask */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_RIS register bit masks
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* @{
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*/
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#define GPTIMER_RIS_TBMRIS 0x00000800 /**< Timer B match raw status */
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#define GPTIMER_RIS_CBERIS 0x00000400 /**< Timer B capture event raw status */
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#define GPTIMER_RIS_CBMRIS 0x00000200 /**< Timer B capture match raw status */
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#define GPTIMER_RIS_TBTORIS 0x00000100 /**< Timer B time-out raw status */
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#define GPTIMER_RIS_TAMRIS 0x00000010 /**< Timer A match raw status */
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#define GPTIMER_RIS_RTCRIS 0x00000008 /**< RTC raw status */
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#define GPTIMER_RIS_CAERIS 0x00000004 /**< Timer A capture event raw status */
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#define GPTIMER_RIS_CAMRIS 0x00000002 /**< Timer A capture match raw status */
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#define GPTIMER_RIS_TATORIS 0x00000001 /**< Timer A time-out raw status */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_MIS register bit masks
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* @{
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*/
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#define GPTIMER_MIS_TBMMIS 0x00000800 /**< Timer B match masked status */
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#define GPTIMER_MIS_CBEMIS 0x00000400 /**< Timer B capture event masked status */
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#define GPTIMER_MIS_CBMMIS 0x00000200 /**< Timer B capture match masked status */
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#define GPTIMER_MIS_TBTOMIS 0x00000100 /**< Timer B time-out masked status */
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#define GPTIMER_MIS_TAMRIS 0x00000010 /**< Timer A match masked status */
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#define GPTIMER_MIS_RTCMIS 0x00000008 /**< RTC masked status */
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#define GPTIMER_MIS_CAEMIS 0x00000004 /**< Timer A capture event masked status */
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#define GPTIMER_MIS_CAMMIS 0x00000002 /**< Timer A capture match masked status */
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#define GPTIMER_MIS_TATOMIS 0x00000001 /**< Timer A time-out masked status */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_ICR register bit masks
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* @{
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*/
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#define GPTIMER_ICR_WUECINT 0x00010000 /**< write update error int clear */
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#define GPTIMER_ICR_TBMCINT 0x00000800 /**< Timer B match int clear */
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#define GPTIMER_ICR_CBECINT 0x00000400 /**< Timer B capture event int clear */
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#define GPTIMER_ICR_CBMCINT 0x00000200 /**< Timer B capture match int clear */
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#define GPTIMER_ICR_TBTOCINT 0x00000100 /**< Timer B time-out int clear */
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#define GPTIMER_ICR_TAMCINT 0x00000010 /**< Timer A match int clear */
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#define GPTIMER_ICR_RTCCINT 0x00000008 /**< RTC interrupt clear */
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#define GPTIMER_ICR_CAECINT 0x00000004 /**< Timer A capture event int clear */
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#define GPTIMER_ICR_CAMCINT 0x00000002 /**< Timer A capture match int clear */
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#define GPTIMER_ICR_TATOCINT 0x00000001 /**< Timer A time-out int clear */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAILR register bit masks
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* @{
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*/
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#define GPTIMER_TAILR_TAILR 0xFFFFFFFF /**< A interval load register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBILR register bit masks
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* @{
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*/
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#define GPTIMER_TBILR_TBILR 0x0000FFFF /**< B interval load register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAMATCHR register bit masks
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* @{
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*/
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#define GPTIMER_TAMATCHR_TAMR 0xFFFFFFFF /**< Timer A match register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBMATCHR register bit masks
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* @{
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*/
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#define GPTIMER_TBMATCHR_TBMR 0x0000FFFF /**< Timer B match register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAPR register bit masks
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* @{
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*/
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#define GPTIMER_TAPR_TAPSR 0x000000FF /**< Timer A prescale */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBPR register bit masks
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* @{
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*/
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#define GPTIMER_TBPR_TBPSR 0x000000FF /**< Timer B prescale */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAPMR register bit masks
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* @{
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*/
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#define GPTIMER_TAPMR_TAPSR 0x000000FF /**< Timer A prescale match */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBPMR register bit masks
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* @{
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*/
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#define GPTIMER_TBPMR_TBPSR 0x000000FF /**< Timer B prescale match */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAR register bit masks
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* @{
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*/
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#define GPTIMER_TAR_TAR 0xFFFFFFFF /**< Timer A register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBR register bit masks
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* @{
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*/
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#define GPTIMER_TBR_TBR 0x0000FFFF /**< Timer B register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAV register bit masks
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* @{
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*/
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#define GPTIMER_TAV_TAV 0xFFFFFFFF /**< Timer A register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TBV register bit masks
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* @{
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*/
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#define GPTIMER_TBV_PRE 0x00FF0000 /**< Timer B prescale register */
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#define GPTIMER_TBV_TBV 0x0000FFFF /**< Timer B register */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_RTCPD register bit masks
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* @{
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*/
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#define GPTIMER_RTCPD_RTCPD 0x0000FFFF /**< RTC predivider */
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/** @} */
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/*---------------------------------------------------------------------------*/
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/** \name GPTIMER_TAPS register bit masks
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* @{
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||
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|
*/
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||
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#define GPTIMER_TAPS_PSS 0x0000FFFF /**< Timer A prescaler */
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||
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|
/** @} */
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||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** \name GPTIMER_TBPS register bit masks
|
||
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|
* @{
|
||
|
|
*/
|
||
|
|
#define GPTIMER_TBPS_PSS 0x0000FFFF /**< Timer B prescaler */
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||
|
|
/** @} */
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** \name GPTIMER_TAPV register bit masks
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define GPTIMER_TAPV_PSV 0x0000FFFF /**< Timer A prescaler value */
|
||
|
|
/** @} */
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** \name GPTIMER_TBPV register bit masks
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define GPTIMER_TBPV_PSV 0x0000FFFF /**< Timer B prescaler value */
|
||
|
|
/** @} */
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** \name GPTIMER_PP register bit masks
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define GPTIMER_PP_ALTCLK 0x00000040 /**< Alternate clock source */
|
||
|
|
#define GPTIMER_PP_SYNCNT 0x00000020 /**< Synchronized start */
|
||
|
|
#define GPTIMER_PP_CHAIN 0x00000010 /**< Chain with other timers */
|
||
|
|
#define GPTIMER_PP_SIZE 0x0000000F /**< Timer size */
|
||
|
|
/** @} */
|
||
|
|
|
||
|
|
#endif /* GPTIMER_H_ */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
* @}
|
||
|
|
*/
|